Control / Status Registers Definition - SeaLevel Route 56 User Manual

Control / Status Registers Definition

The I/O register base address is selected by SW1. The address range is 200H to 3FFH. The control / status registers
occupies 8 consecutive locations. The following tables provide a functional description of the bit positions.
X = do not care { }= always this value
Address Mode D7
Base+0 RD MEMEN
Base+0 WR MEMEN
Base+1 RD {0}
Base+1 WR INT2
Base+2 RD {0}
Base+2 WR X
Base+3 RD {0}
Base+3 WR Software board reset
Base+4 RD SHARE
Base+4 WR SHARE
Base+5 RD LL
Base+5 WR LL
Base+6 RD SD7
Base+7 RD SD15
Sealevel Systems ROUTE 56
Technical Description
D6 D5 D4
IUSCEN {0} {0}
IUSCEN X X
{0} {0} MA18
INT1 INT0 MA18
WSEN {1} {0}
WSEN X X
{0} INTPEND RESTAT
X X X
IRQEN {0} {0}
X X X
RL {0} IFSEL
RL X IFSEL
SD6 SD5 SD4
SD14 SD13 SD12
D3 D2 D1
P17 P16 P15
P17 P16 P15
MA17 MA16 MA15
MA17 MA16 MA15
{0} {0} {0}
X X X
{1} {0} {0}
X X X
{0} {0} {0}
X X X
M3 M2 M1
M3 M2 M1
SD3 SD2 SD1
SD11 SD10 SD9
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D0
P14
P14
MA14
MA14
{0}
X
{0}
X
{0}
X
M0
M0
SD0
SD8