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Technical Description
IUSC™
The ROUTE 56 adapter is based on a single Zilog Z16C32 IUSC (Integrated
Universal Serial Controller). Application and driver software access the IUSC
registers through the first 256 bytes of on-board RAM. Register access to the
IUSC can be disabled via I/O registers allowing the first 256 bytes of RAM to
be used for buffer storage. The IUSC has a built-in DMA controller that allows
high-speed data transfers directly to and from the 256K block of on-board
memory. The IUSCs built-in DMA controller supports 4 different modes of
DMA transfer: Single Buffer, Pipelined, Array, and Link List. An on-board
16MHz oscillator clocks the IUSC.
RAM
The ROUTE 56 has 256K of on-board SRAM. The 256K bytes of SRAM
appear to the host processor in the 2nd 512K bytes of the host's memory
address range, (Segment 80000 to F0000). This 256K of SRAM is in a 16K
bank-switched window. The address of the 16K window and the page is
software selectable. The IUSC always views the 256K of SRAM as linear
memory. The SRAM can be selectively disabled through software. The SRAM
should be addressed in a section that does not conflict with system memory
(i.e. I/O adapters, Video Memory, BIOS/BIOS extensions.)
1 MB (FFFFF)
16K Address Window
for Bank Switching
(D0000-D4000)
512K (80000)
Low Address Mode
Selected
Sealevel Systems ROUTE 56
Page 7
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