Technical Description; Features; Internal Baud Rate Generator; I/O Registers Definition - Control And Status - SeaLevel ACB-232.LPCI User Manual

The ACB-232.LPCI utilizes the Zilog 85230 Enhanced Serial Communications Controller (ESCC). This chip
features programmable baud rate, data format and interrupt control. Refer to the ESCC Users Manual for details on
programming the 85230 ESCC chip.

Features

•
One channel of synchronous or asynchronous communications using the Zilog Z85230 chip
•
EIA/TIA-232 Signals supported TD, RD, CTS, RTS, DCD, DSR, DTR, TXC, RXC, TSET, RI
•
Programmable options for Transmit clock as input or output
•
Software programmable baud rate

Internal Baud Rate Generator

The baud rate of the ESCC is programmed under software control. The standard oscillator supplied with the board is
7.3728 MHz. However, other oscillator values can be substituted to achieve different baud rates.

I/O Registers Definition - Control and Status

The control and status registers occupy 16 consecutive locations. The following tables provide a functional
description of the bit positions.
X = do not care
Address Mode D7
Base+4 RD {0}
Base+4 WR X
Base+5 RD {0}
WR X
Base+5
Base+6 RD {0}
WR X
Base+6
Base+14 RD SD7
RD SD15
Base+15
Field
IRQST SCC interrupt status: 1 = No interrupt pending on IUSC;
SYNCA _RTS – 0 = SYNCA is high, 1 = SYNCA connected to RTS ( 0 on power up )
SYNCA_RTS
SYNCA_CTS SYNCA_CTS – 0 = SYNCA is high, 1 = SYNCA connected to CTS
TSETSLA CHAN A – TSET clock source 0 = TRXCA as source,
RXCOPTA RXCOPTA – 0 = selects received RXC for RTXCA,
DSROUT DSROUT – 0 = DSR not routed to SCC
RIOUT RIOUT – 0 = RI not routed to SCC
TXOUT TXOUT – 0 = TXD routed from SCC to 1488
Optional security feature. Unique value per customer or application. ( default value = FFFF)
SD0-SD15
* DSR- is connected to Port B DCD on the 85230 only when this bit is set to a 1. If 9015 compatibility is
required, this bit must be set as part of the SCC initialization.
** RI- is connected to Port B CTS on the 85230 only when this bit is set to a 1. If 9015 compatibility is required,
this bit must be set as part of the SCC initialization.
Sealevel Systems ACB-MP.PCI

Technical Description

{ }= always this value
D6 D5
IRQST {0}
X X
{0} SYNCA_RTS
X SYNCA_RTS
{0} {0}
X X
SD6 SD5
SD14 SD13
D4 D3
{0} {0}
X X
SYNCA_CTS {0}
SYNCA_CTS X
TXOUT RIOUT
TXOUT RIOUT
SD4 SD3
SD12 SD11
Description
Base +4
0 = Interrupt pending on IUSC.
Base +5
Base +6
1= received TXC as source ( 0 on power up )
1 = selects SCC PCLK for RTXCA ( 0 on power up )
1 = DSR routed to SCC DCDB (0 on power up)*
1 = RI routed to SCC CTSB (0 on power up)**
1 = Forces TXD always a high (for idle mark bug in ESCC)***
Base +14 and 15
Technical Description
D2 D1
{0} {0}
X X
{0} {0}
X X
DSROUT TSETSLA
DSROUT TSETSLA
SD2 SD1
SD10 SD9
( 0 on power up )
Page 2
D0
{0}
X
{0}
X
RXCOPTA
RXCOPTA
SD0
SD8