SeaLevel Route 56 User Manual page 12

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Field
Description
MEMEN
1 = Host access to RAM or IUSC enabled; 0 = Host access to RAM or IUSC disabled.
IUSCEN
1 = Enable Host access to RAM; 0 = Enable Host access to IUSC.
P17-P14
These bits select which of sixteen 16K ram pages is visible at the address selected by MA18-MA14.
MA18-14
These bits select the base memory address of the 16K bank-switched window of the 256K SRAM.
INT2-INT0
Interrupt: 000 = Interrupts disabled, Interrupts enabled for all other values 001-111.
IRQEN
1 = Interrupts enabled, 0 = Interrupts disabled (Status Bit, Read Only)
SHARE
1= IRQ sharing enabled ;0= IRQ sharing disabled. ( 0 on power up)
INTPEND
IUSC interrupt status: 1 = No interrupt pending on IUSC; 0 = Interrupt pending on IUSC.
RESTAT
Reset status: 1 = On-board reset inactive; 0 = On-board reset active.
WSEN
Wait State Enable: 1 = disable wait states (Zero wait states); 0 = enable wait states. ( 0 on power up )
RL
Remote loopback
LL
Local loopback
IFSEL
0 = DIP-switch interface select, 1 = Base+5 register M3-M0 interface select. ( 0 on power up )
M0-M3
I/O mode select to SP505
If IFSEL = 0, the value read is equal to the switch setting
If IFSEL = 1, the value read is the value written
See table for valid interface options
SD0-SD15
Optional security feature. Unique value per customer or application. ( default value = FFFF)
Sealevel Systems ROUTE 56
Technical Description
Page 9

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