Cmos Ram Map - DIGITAL-LOGIC MICROSPACE PCC-P5 Technical User's Manual

DIGITAL-LOGIC AG
4.6.3

CMOS RAM Map

Systems based on the industry-standard specification include a battery backed Real
Time Clock chip. This clock contains at least 64 bytes of non-volatile RAM. The sys-
tem BIOS uses this area to store information including system configuration and ini-
tialization parameters, system diagnostics, and the time and date. This information
remains intact even when the system is powered down.
The BIOS supports 128 bytes of CMOS RAM. This information is accessible through
I/O ports 70h and 71h. CMOS RAM can be divided into several segments:
§
Locations 00h - 0Fh contain real time clock (RTC) and status information
§
Locations 10h - 2Fh contain system configuration data
§
Locations 30h - 3Fh contain System BIOS-specific configuration data as well as chipset-specific in-
formation
§
Locations 40h - 7Fh contain chipset-specific information as well as power management configuration
parameters
The following table provides a summary of how these areas may be further divided.
Beginning Ending
00h 0Fh
10h 2Dh
2Eh 2Fh
30h 33h
34h 3Fh
40h 5Bh
5Ch 5Dh
5Eh 6Eh
6Fh 7Dh
7Eh 7Fh
Checksum Description
No RTC and Checksum
Yes System Configuration
No Checksum Value of 10h - 2Dh
No Standard CMOS
No Standard CMOS - SystemSoft Reserved
Yes Extended CMOS - Chipset Specific
No Checksum Value of 40h - 5Bh
No Extended CMOS - Chipset Specific
Yes Extended CMOS - Power Management
No Checksum Value of 6Fh - 7Dh
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PCCP5 Manual V2.3