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DIGITAL-LOGIC AG
PCCP5 Manual V2.3
3
T
ISA
PC/104 B
HE
AND
US SIGNALS
AEN, output
Address Enable is used to degate the microprocessor and other devices from the I/O channel to allow DMA
transfers to take place. low = CPU Cycle , high = DMA Cycle
BALE, output
Address Latch Enable is provided by the bus controller and is used on the system board to latch valid a d-
dresses and memory decodes from the microprocessor. This signal is used so that devices on the bus can
latch LA17..23. The SA0..19 address lines latched internally according to this signal. BALE is forced high
during DMA cycles.
/DACK[0..3, 5..7], output
DMA Acknowledge 0 to 3 and 5 to 7 are used to acknowledge DMA requests (DRQO through DRQ7). They
are active low. This signal indicates that DMA operation can begin.
DRQ[0..3, 5..7], input
DMA Requests 0 through 3 and 5 through 7 are asynchronous channel requests used by peripheral devices
and the I/O channel microprocessors to gain DMA service (or control of the system). A request is generated
by bringing a DRQ line to an active level. A DRQ line must be held high until the corresponding DMA R e-
quest Acknowledge (DACK/) line goes active. DRQO through DRQ3 will perform 8-bit DMA transfers; DRQ5-
7 are used for 16 accesses.
/IOCHCK, input
IOCHCK/ provides the system board with parity (error) information about memory or devices on the I/O
channel. low = parity error , high = normal operation
IOCHRDY, input
I/O Channel Ready is pulled low (not ready) by a memory or I/O device to lengthen I/O or memory cycles.
Any slow device using this line should drive it low immediately upon detecting its valid address and a Read
or Write command. Machine cycles are extended by an integral number of one clock cycle (67 nanosec-
onds). This signal should be held low for no more than 2.5 microseconds. low = wait, high = normal opera-
tion
/IOCS16, input
I/O 16 bit Chip Select signals the system board that the present data transfer is a 16-bit, 1 wait-state, I/0 cy-
cle. It is derived from an address decode. /IOCS16 is active low and should be driven with an open collector
(300 ohm pull-up) or tri-state driver capable of sinking 20mA. The signal is driven based only on SA15-SAO
(not /IOR or /IOW) when AEN is not asserted. In the 8 bit I/O transfer, the default transfers a 4 wait-state cy-
cle.
/IOR, input/output
I/O Read instructs an I/O device to drive its data onto the data bus. It may be driven by the system micro-
processor or DMA controller, or by a microprocessor or DMA controller resident on the I/O channel. This sig-
nal is active low.
/IOW, input/output
I/O Write instructs an I/O device to read the data on the data bus. It may be driven by any microprocessor or
DMA controller in the system. This signal is active low .
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