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NAME
0x18
DCOcodeLSB
0x19 Reserved
0x1A
Status
0x1B
ResetEvent
0x1C
WDogCode
0x1D
WDogPeriod
0x1E Reserved
0x1F Factory Test
SH3000UM version 0.95
Copyright ©2002 Semtech Corporation
Table 9: SH3000 MicroBuddy™ Registers 0x18 to 0x1F
Control and Status Registers
RESET
RESET
EVENT
VALUE
b7 Reserved, not used
-0-
P W B
1 b6
P W B
0 b5
P W B
0 b4
0x40
P W B
0 b3
P W B
0 b2
P W B
0 b1
P W B
0 b0
P W B
0
b7 Xtal oscillator is stable
b6
-0-
b5
-0-
P W B
0
b4 Auto CLK shut-down mode (transitions on CLK
0x00
P W B
0
b3 Backup battery low.
P W B
0
b2 Serial I/O parity error.
P W B
0
b1 Interrupt status (1 = pending, 0 = idle).
P W B
0
b0 FLL locked (1 = locked, 0 = unlocked).
b7
-0-
b6
-0-
0x02
b5
-0-
0x04
b4
-0-
0x08
P
B
0/1 b3 V
or
W
0/1 b2 Watchdog code violation caused the reset.
0x09
W
0/1 b1 Watchdog timeout caused the reset.
P
0/1 b0 Power-on caused the reset.
P W B 0x00
b7 Reserved, not used
-0-
P W B
0
b6
P W B
0
b5
P W B
0
b4
0x00
P W B
0
b3
P W B
0
b2
P W B
0
b1
P W B
0
b0
2002-08
DESCRIPTION
DCO setting,
least-significant bits 0:6
Reserved, not used
Reserved, not used
Reserved, not used
dropped below V
threshold (brown-out).
DD
BO
Alternate writes of code-Bytes 0x5A and 0xC3 are required
to prevent timeout. Watchdog is reloaded after every write
(only one code has to be written to reload the watchdog, but
the value of the code-Byte has to alternate between 0x5A
and 0xC3).
Watchdog timeout value. Depending on WdogClkSelect bit
in the Config register (R0x0E, b2), the watchdog will be
decremented by either a 32 kHz clock or the signal on the
CLK
pin (in which case the watchdog will be suspended
OUT
when the HFCLK stops). The Watchdog is disabled after the
reset and started by writing to WDogPeriod. Once started,
the clock selection or timeout value cannot be changed.
Reserved, not used
Reserved,
do not write to this register.
SH3000 User Manual
Preliminary
detected).
IN
37
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