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3. High-Frequency (HF) Oscillator
The frequency synthesizer in the SH3000 is constructed from the 2:1 digitally-tunable 8.0–16.0 MHz High-
Frequency (HF) oscillator followed by a programmable binary post-divider; see Figure 5.
32.768 kHz
Frequency Locked Loop
2048 Hz
/16
From / To
Serial I/O
The Clock Source selector and the programmable Post-scaler allow instantaneous switching between
the 32 kHz internal clock and the divided-down HF oscillator output. There is no settling or instability when
the switch occurs.
The SH3000 employs a Frequency Locked Loop (FLL) to synchronize the HF clock to the 32 kHz
reference. This architecture has several advantages over the common PLL (Phase Lock Loop) systems,
including the ability to stop and re-start without frequency transients and instability, and with instant settling
to a correct frequency. The conventional PLL approach invariably includes a low-pass filter that requires a
long settling time on restart.
When the HF oscillator is operating without FLL control, it can set the frequency of the clock on the
CLK
pin to ±0.025%, and maintain it to ±0.5% over temperature.
OUT
When the HF oscillator is operating under FLL control, the absolute accuracy and stability of the HF clock
depends on the quality of the 32.768 kHz internally generated clock. An external 32.768 kHz watch crystal
used as a reference provides excellent accuracy and stability for the SH3000.
The primary purpose of the FLL is the maintenance of the correct frequency while the ambient
temperature is changing. As the temperature drift of the HF oscillator is quite small, any corrective action
from the FLL system is also small and gradual, in proportion with the changes in temperature.
To set a new frequency for the FLL, the host microcontroller writes the 13-bit Frequency Set value to the
appropriate bits in registers SS_FreqSet (R0x15) and FreqSetLSB (R0x16); it may also update the post-
scaler setting in the WP_PostScale register (R0x17). The resulting output frequency is calculated using
simple formulas [1] and [2] (reference frequency is 32.768 kHz):
F
= 2048 Hz * (Frequency Set value + 1) [1]
OSC
F
= F
/ (Post-divider setting) [2]
OUT
OSC
SH3000UM version 0.95
Copyright ©2002 Semtech Corporation
FLL Enable
Logic
13-bit
Frequency
Set value
Figure 5: High-Frequency (HF) Oscillator
2002-08
Clock Source
Post-scaler
(Divide by 1, 2, 4,
8, 16, 32, 64, 128)
18-bit
DCO Code
Register
8-bit Pseudo
Spectrum
Random Noise
Spreading
Generator
Controls
SH3000 User Manual
Preliminary
Clock On
CLK
OUT
1
Clock Buffer
16
0
and Glue
CLK
IN
Logic
15
S
/S
TART
TOP
Force
HF Digitally
DCO On
Controlled
Oscillator
8-16 MHz
10
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