Table 6: Minimum/Maximum Serial Bit Timing - Semtech SH3000 User Manual

The interface is self-timed based on the duration of the start bit field, and communication can take place
whenever CLK is active, either at 32 kHz or at a higher frequency. If the host microcontroller is
OUT
running synchronously to the CLK
then a minimum of 4 CLK
serial interface is asynchronous to CLK
maximum of 1024 CLK
OUT
Table 6 displays the minimum and maximum bit periods for the serial communications for CLK
frequencies of 16 MHz, 8 MHz, and 2 MHz.
CLK
Frequency
16 MHz
8 MHz
2 MHz
SH3000UM version 0.95
Copyright ©2002 Semtech Corporation
generated by the SH3000 (which should generally be the case),
OUT
cycles per bit are required to maintain communication integrity. If the host's
OUT
, then a minimum of 52 cycles per bit are necessary. A
OUT
cycles per bit field is supported.

Table 6: Minimum/Maximum Serial Bit Timing

Minimum Bit
OUT
Period
(host
synchronous
CLK
to )
OUT
250 ns
500 ns
2 ms
2002-08
Minimum Bit Maximum Bit
Period Period
(host
asynchronous
CLK
to )
OUT
1.625 ms 32 ms
3.25 ms 63.9 ms
13 ms 255 ms
SH3000 User Manual
Preliminary
OUT
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