Watchdog Timer - Semtech SH3000 User Manual

2.2 Watchdog Timer

The Watchdog Timer is part of the CPU Supervisor function of the SH3000. Whereas the low-V
Brownout Detector monitors supply voltage, the watchdog timer monitors behavior of the host
microcontroller. It is based on a programmable timer that must be restarted periodically by the host. If the
host does not send a command to restart the timer (which is likely when the host firmware has hung or
failed), the watchdog resets the host.
The watchdog is disabled after reset occurs. It stays disabled until initialized by the host microcontroller.
The initialization requires the watchdog clock mode to be selected (see Figure 2) and the 7-bit time-out
value to be set. Once the time-out value is written, the watchdog begins operations and cannot be
stopped; the time-out value and clock source can no longer be changed.
The two clock sources available for the watchdog are the internal 32 kHz clock and the CLK
The time-out interval can be set with bits 0:6 of the WdogPeriod register (R0x1D). When operating from
the 32 kHz source, the time-out interval is programmable from 7.8125 ms to 1000 ms with a resolution of
7.8125 ms. Since the internal 32 kHz clock is running all the time, the time-out period is fixed and
predictable.
When operating from the CLK
cycles with a resolution of 256 cycles. The actual time-out duration is variable; it depends both on the
frequency of CLK and the amount of time the host microcontroller spends in the STOP mode, when
OUT
the CLK signal is also stopped. When the CLK
OUT
These two clock modes, together with the programmable time-out value, allow the SH3000 exceptional
flexibility previously unattainable by discrete watchdog solutions.
The watchdog timer is kept from timing out by periodic writing of a code to the WdogCode register
(R0x1C). As a safety measure, the code values must be alternated between 0x5A and 0xC3. The first
code written to the register must be 0x5A; at the next period, the code 0xC3 must be used, and so forth.
The timer is reloaded after every write of the correct one of these codes.
If the watchdog code is not written before the time-out period expires, or if the code is incorrect or out of
sequence, the SH3000 issues a reset to the microcontroller by asserting both the RST (pin 11) and
(pin 10) lines. The reset state is asserted for 6 ms.
SH3000UM version 0.95
Copyright ©2002 Semtech Corporation
signal, the time-out period is programmable between 256 and 32768
OUT
OUT
2002-08
SH3000 User Manual
signal is stopped, the watchdog is suspended.
Preliminary
DD
signal.
OUT
RST
N
7