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Control, Setting, and Calibration Registers Initialized from OTP Memory (continued)
NAME
0x15
0 SS_FreqSet
0x16
0 FreqSetLSB
0x17
0 WP_PostScale
0x10
1 ID_RAM_MSB
0x11 1 Reserved
0x12
1 ID_RAM_2
0x13 1 Reserved
0x14
1 ID_RAM_1
0x15 1 Reserved
0x16
1 ID_RAM_LSB
0x17 1 Reserved
SH3000UM version 0.95
Copyright ©2002 Semtech Corporation
INIT
INIT
WRITE
EVENT
VALUE
PROTECT
P W B
?
P W B
?
P W B
?
P W B
?
0x??
P W B
?
P W B
?
P W B
?
P W B
?
P W B 0x??
P W
?
P W
?
P W
?
P W
?
0x??
P W B
?
P W B
?
P W B
?
P W B
?
P W B 0x??
I
P W B 0x??
I
P W B 0x??
I
P W B 0x??
I
2002-08
DESCRIPTION
A
b7
Amount of HFCLK Spectrum
Spreading, 4 (four) settings.
A
b6
A
b5
EnableSS, enable spectrum spreading.
A
b4
A
b3
Frequency Set Value for FLL, most-
A
b2
significant bits 8:12
A
b1
A
b0
Frequency Set Value for FLL, bits 0:7.
A
IDCode Write Protect, 1 = no writes.
b7
b6
Calibration Write Protect, 1 = no writes.
Application Write Protect, 1 = no writes.
b5
V
Value Write Protect, 1 = no writes.
b4
BO
A
b3
CLK32 enable, 1 = enable, 0 = disable.
A
b2
DCO Post-Scaler, 8 (eight) setting:
A
b1
/1, 2, 4, 8, 16, 32, 64, 128.
A
b0
General-purpose RAM, bits 24:31,
bits 24:31 of ID code are loaded on
initialization.
Reserved, not used.
General-purpose RAM, bits 16:23,
bits 16:23 of ID code are loaded on
initialization.
Reserved, not used.
General-purpose RAM, bits 8:15,
bits 08:15 of ID code are loaded on
initialization.
Reserved, not used.
General-purpose RAM, bits 0:7,
bits 00:07 of ID code are loaded on
initialization.
Reserved, not used.
SH3000 User Manual
Preliminary
36
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