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Note: The four bit flags 0:3 (Power-on reset, watchdog code violation, watchdog timeout, and brownout) in
the ResetEvent register (R0x1B) reflect reset history. This register is readable, and may be cleared
individually by writing a "1" to the relevant bit position; they are not cleared automatically. On a power-on
reset (bit 0), the brownout flag (bit 3) is invariably set also.
NAME
0x1B
ResetEvent
0x1C
WDogCode
0x1D
WDogPeriod
SH3000UM version 0.95
Copyright ©2002 Semtech Corporation
RESET
RESET
EVENT
VALUE
b7
-0-
b6
-0-
Reserved, not used
0x02
b5
-0-
0x04
b4
-0-
0x08
P
B
0/1 b3 V
DD
or
W
0/1 b2 Watchdog code violation caused the reset.
0x09
W
0/1 b1 Watchdog timeout caused the reset.
P
0/1 b0 Power-on caused the reset.
Alternate writes of code-Bytes 0x5A and 0xC3 are required
to prevent timeout. Watchdog is reloaded after every write
P W B 0x00
(only one code has to be written to reload the watchdog, but
the value of the code-Byte has to alternate between 0x5A
and 0xC3).
b7 Reserved, not used
-0-
P W B
0
b6
Watchdog timeout value. Depending on WdogClkSelect bit
P W B
0
b5
in the Config register (R0x0E, b2), the watchdog will be
P W B
0
b4
decremented by either a 32 kHz clock or the signal on the
0x00
CLK
P W B
0
b3
when the HFCLK stops). The Watchdog is disabled after the
P W B
0
b2
reset and started by writing to WDogPeriod. Once started,
P W B
0
b1
the clock selection or timeout value cannot be changed.
P W B
0
b0
2002-08
SH3000 User Manual
DESCRIPTION
dropped below V
threshold (brown-out).
BO
pin (in which case the watchdog will be suspended
OUT
Preliminary
9
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