Figure 3: Operation Of Low; Figure 4: Noise Filtering - Semtech SH3000 User Manual

When a brownout event occurs, the SH3000 continues to provide the clock to the host microcontroller, but
at a reduced frequency between 500 kHz and 1.0 MHz. After a delay of 2 ms this clock is stopped,
automatically lowering the energy consumption of the whole system; see Figure 3.
A noise filter prevents the reset lines from going active due to noise and power glitches on the V
Figure 4 shows typical behavior for the V
duration and amplitude.
V + V
BO HYST
V
BO
V
DD
1V
3-5ms
RST
Undefined
RST
N
1ms
Normal
CLK
OUT
F
OUT
Figure 3: Operation of Low V
When V power is removed from the chip, the following sequence of events occurs:
DD
1. When V drops below the programmed reset threshold,
DD
reset lines are guaranteed to become active within 5 µs after V
2. If V is above 1.5 V to 2.2 V, then the chip switches on to V
BATT
remain asserted
3. CLK continues to run at a reduced rate (500 kHz to 1 MHz), provided that V
OUT
approximately 2.25 V. If V
immediately. If CLK
time.
4. If enabled, the CLK32 output continues normal operations when V
is available.
5. 2 ms after V drops below the V
DD
The four bit flags 0:3 (Power-on reset, watchdog code violation, watchdog timeout, and brownout) in the
ResetEvent register (R0x1B) reflect reset history. This register is readable, and may be cleared
individually by writing a "1" to the relevant bit position; they are not cleared automatically. On a power-on
reset (bit 0), the brownout flag (bit 3) is invariably set also.
SH3000UM version 0.95
Copyright ©2002 Semtech Corporation
level just above V
DD
12ms minimum
6ms
2ms 2ms
Reduced F
OUT
0.5-1.0 MHz
/ Brownout Detector
DD
falls below this threshold at any time, then CLK
DD
was inactive when the reset condition occurred, it is activated at this
OUT
threshold, CLK
BO
2002-08
SH3000 User Manual
for negative-going spikes of various
BO
10
5
Guaranteed NO reset
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Am plitude, V

Figure 4: Noise Filtering

RST and RST are asserted. Both
N
has crossed the V
DD
operation;
BATT
is absent and backup power
DD
switches off.
OUT
Preliminary
line.
DD
Duration
Guaranteed reset
threshold.
BO
RST and RST
N
stays above
DD
is stopped
OUT
6