Semtech SH3000 User Manual

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SH3000 User Manual

Preliminary

Using the SH3000 MicroBuddy™

SH3000UM version 0.95

2002-08

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Summary of Contents for Semtech SH3000

Page 2 SH3000 User Manual Preliminary MicroBuddy, mBuddy, and mB are trademarks of Semtech Corporation. Semtech is a registered trademark of Semtech Corporation. All other trademarks are the property of their respective owners. SH3000UM version 0.95 2002-08 Copyright ©2002 Semtech Corporation...
Page 3 SH3000 User Manual Preliminary Document Revision History Revision Date Reason for Changes Rev. 0.95 2002-08-09 Preliminary draft SH3000UM version 0.95 2002-08 Copyright ©2002 Semtech Corporation...
Page 4: Table Of Contents
SH3000 User Manual Preliminary Table of Contents Introduction ............................1 CPU Supervisor ............................. 4 Low V Reset ..........................5 Watchdog Timer ..........................7 CPU Supervisor Registers ......................8 High-Frequency (HF) Oscillator ......................10 Auto Clock Detect Mode ....................... 12 Programmable Spread Spectrum ....................13 High-Frequency (HF) Oscillator Registers..................
Page 5 Table 5: Load Capacitance Settings ......................18 Table 6: Minimum/Maximum Serial Bit Timing..................26 Table 7: SH3000 MicroBuddy™ Registers 0x00 to 0x0F................34 Table 8: SH3000 MicroBuddy™ Registers 0x10 to 0x17 ................35 Table 9: SH3000 MicroBuddy™ Registers 0x18 to 0x1F................37 List of Figures Figure 1: SH3000 MicroBuddy™...
Page 7: Introduction
(with both permanent write-inhibit and lock/unlock capabilities). A backup power source may also be connected to the SH3000. The IC can directly accommodate 2/3-cell zinc-carbon/alkaline, 2/3-cell mercury, 2/3/4-cell NiCd/NiMH, 1-cell Li/Li+ batteries, or a super cap.
Page 8: Figure 1: Sh3000 Microbuddy™ Block Diagram
Monitor & Logic LF Oscillator Watchdog Oscillator Control Logic Real Time Clock Select Logic Periodic Interrupt Interrupt / Wake-up Timer IO/I Serial I/O Oscillator SH3000 µBuddy™ Figure 1: SH3000 MicroBuddy™ Block Diagram SH3000UM version 0.95 2002-08 Copyright ©2002 Semtech Corporation...
Page 9: Table 1: Sh3000 Microbuddy™ Pin Descriptions
32 kHz crystal oscillator (CLK is connected to ). The SH3000 always starts up using the internal 32 kHz RC oscillator. If Digital In is high, the internal 32 kHz clock switches to the crystal oscillator once it has stabilized, and RC oscillator is disabled for power conservation.
Page 10: Cpu Supervisor
The SH3000 has both active high and active low reset output pins. Both are driven strong in the active state, and weak in the inactive state. This eliminates the need for external pull-ups and allows various reset sources to be connected together in a wire-OR configuration.
Page 11: Low Vdd Reset
6 ms, but no less than 12 ms from the moment brownout has been detected. Such a fast reset is possible because the SH3000 provides a fast-starting clock that is free of crystal start- up time delays. This gives the SH3000 an advantage over other external reset circuits, which must have a long reset pulse duration to accommodate long and unpredictable crystal start-up times.
Page 12: Figure 3: Operation Of Low
SH3000 User Manual Preliminary When a brownout event occurs, the SH3000 continues to provide the clock to the host microcontroller, but at a reduced frequency between 500 kHz and 1.0 MHz. After a delay of 2 ms this clock is stopped, automatically lowering the energy consumption of the whole system;...
Page 13: Watchdog Timer
If the watchdog code is not written before the time-out period expires, or if the code is incorrect or out of sequence, the SH3000 issues a reset to the microcontroller by asserting both the RST (pin 11) and (pin 10) lines. The reset state is asserted for 6 ms.
Page 14: Cpu Supervisor Registers
SH3000 User Manual Preliminary 2.3 CPU Supervisor Registers RESET RESET EVENT VALUE NAME DESCRIPTION b7 XTALtune Rewrite-Once Enable (see notes for use) P W B 0 b6 Register Page for R0x10 through R0x17. 0 =Page0, 1 =Page1. P W B 0 b5 ForceDCOon.
Page 15 SH3000 User Manual Preliminary Note: The four bit flags 0:3 (Power-on reset, watchdog code violation, watchdog timeout, and brownout) in the ResetEvent register (R0x1B) reflect reset history. This register is readable, and may be cleared individually by writing a “1” to the relevant bit position; they are not cleared automatically. On a power-on reset (bit 0), the brownout flag (bit 3) is invariably set also.
Page 16: High-Frequency (Hf) Oscillator
32 kHz internal clock and the divided-down HF oscillator output. There is no settling or instability when the switch occurs. The SH3000 employs a Frequency Locked Loop (FLL) to synchronize the HF clock to the 32 kHz reference. This architecture has several advantages over the common PLL (Phase Lock Loop) systems, including the ability to stop and re-start without frequency transients and instability, and with instant settling to a correct frequency.
Page 17: Table 3: Operating Parameters For Fll
(bit 2) in the FLLcontrol register. The SH3000 performs a successive approximation algorithm on the 7 least significant bits of the 18-bit DCO code value, and finds a locked setting in approximately 5 ms. The clock may experience the maximum frequency fluctuations of only 3.2%.
Page 18: Auto Clock Detect Mode
Force DCO On bit (bit 5) in the Config register (R0x0E). Systems requiring a very stable clock for short periods of time (controlling an integrating D/A converter, for example), may stop the FLL action in the SH3000 by resetting the FLL enable bit (bit 0) in the FLLcontrol register (R0x0F).
Page 19: Programmable Spread Spectrum
Preliminary 3.2 Programmable Spread Spectrum The SH3000 offers a technique for reducing electromagnetic interference (EMI). It can be a part of the initial design strategy, or it can be applied in the prototype stage to fix problems identified during compliance testing. This feature of the SH3000 may greatly reduce the requirements for radio frequency (RF) shielding, and permits the use of simple plastic casings in place of expensive RFI-coated or metal casings.
Page 20: High-Frequency (Hf) Oscillator Registers
SH3000 User Manual Preliminary 3.3 High-Frequency (HF) Oscillator Registers RESET RESET EVENT VALUE NAME DESCRIPTION XTALtune Rewrite-Once Enable (see notes for use) P W B 0 b6 Register Page for R0x10 through R0x17. 0 =Page0, 1 =Page1. P W B 0 b5 ForceDCOon.
Page 21 SH3000 User Manual Preliminary INIT INIT WRITE EVENT VALUE PROTECT NAME DESCRIPTION Adjustment for internal temperature- compensated Voltage Reference, Factory-Only temperature drift trim. 0x13 _DCOcode 0x?? Disconnect Internal R P W B 0=connected, 1 = disconnected. P W B DCO setting, P W B most-significant bits 15:17.
Page 22 SH3000 User Manual Preliminary RESET RESET EVENT VALUE NAME DESCRIPTION b7 Reserved, not used P W B 1 b6 P W B 0 b5 P W B 0 b4 0x18 DCOcodeLSB 0x40 DCO setting, P W B 0 b3 least-significant bits 0:6...
Page 23: Low-Frequency (Lf) Oscillator
V BATT When power is first applied to the SH3000, the RC oscillator takes over. It supplies the 32 kHz clock for start-up and initialization. However, if the CLK pin is set high, then the crystal oscillator is enabled.
Page 24: Low-Frequency (Lf) Oscillator Registers
SH3000 User Manual Preliminary To reprogram the load capacitance, clear the XTALtune Rewrite-Once Enable bit (bit 7) of the Config register (R0x0E) and then immediately set bits 7:4 of the register Xtune_R Adj (R0x12) with the desired value; Table 5 shows the available values.
Page 25 SH3000 User Manual Preliminary INIT INIT WRITE EVENT VALUE PROTECT NAME DESCRIPTION Reserved, not used P W B Interrupt Polarity, 1 = High, 0 = Low. P W B P W B 0x11 0 IPol_RCtune 0x?? P W B 32 kHz RC Oscillator Adjustment, nominal ~330 Hz per step.
Page 26 SH3000 User Manual Preliminary RESET RESET EVENT VALUE NAME DESCRIPTION P W B b7 Xtal oscillator is stable Reserved, not used P W B b4 Auto CLK shut-down mode (transitions on CLK detected). 0x1A Status 0x00 P W B b3 Backup battery low.
Page 27: Real-Time Clock (Rtc)
The RTC registers can be written to in any order. Only when the register RTCsubseconds is written are the entire six byte loaded into the RTC counters. Note: Check the SH3000 Errata document. SH3000UM version 0.95 2002-08 Copyright ©2002 Semtech Corporation...
Page 28: Real-Time Clock (Rtc) Registers
SH3000 User Manual Preliminary 5.1 Real-Time Clock (RTC) Registers RESET RESET EVENT VALUE NAME DESCRIPTION RTCdaysMSB 0x08 0x00 16-bit binary value, 0x0000 to 0xFFFF (0 to 65535, ~ 179.5 years). When RTCsubseconds is 0x09 RTCdaysLSB 0x00 read, all RTC registers are...
Page 29: Periodic Interrupt/Wake-Up Timer
If there is an interrupt pending from the SH3000, and the host microcontroller does not clear the interrupt pending bit, then the SH3000 issues an interrupt after each subsequent read or write cycle until this bit is cleared (see Figure 7).
Page 30: Periodic Interrupt/Wake-Up Timer Registers
SH3000 User Manual Preliminary 6.1 Periodic Interrupt/Wake-up Timer Registers RESET RESET EVENT VALUE NAME DESCRIPTION 0x00 PeriodMSB W B 0x00 Periodic Interrupt / Wake-up Timer setting. 0x01 Period2 W B 0x00 With 32.768 kHz clock the period = (32-bit value)/32768.
Page 31: Serial Interface
For example, if interrupt is programmed to be active low, this pin is weakly pulled to V when inactive. As shown in Figure 8, the SH3000 and the host communicate with serial data streams. The host always initiates communication. A data stream consists of the following (in this order): ·...
Page 32: Table 6: Minimum/Maximum Serial Bit Timing
32 kHz or at a higher frequency. If the host microcontroller is running synchronously to the CLK generated by the SH3000 (which should generally be the case), then a minimum of 4 CLK cycles per bit are required to maintain communication integrity. If the host’s serial interface is asynchronous to CLK , then a minimum of 52 cycles per bit are necessary.
Page 34: Interrupt Interface
SH3000 User Manual Preliminary 7.2 Interrupt Interface The serial communications line to the SH3000 (Pin 14, IO/I ) also serves as the interrupt to the host microcontroller. The polarity of the interrupt is software programmable using the interrupt polarity bit (bit 6) of the IPol_RCtune register (R0x11).
Page 35 SH3000 User Manual Preliminary RESET RESET EVENT VALUE NAME DESCRIPTION P W B b7 Xtal oscillator is stable Reserved, not used P W B b4 Auto CLK shut-down mode (transitions on CLK detected). 0x1A Status 0x00 P W B b3 Backup battery low.
Page 36: Auxiliary Functions
Four bytes of general-purpose RAM reside at addresses R0x00, R0x12, R0x14, and R0x16 on page 1 in the SH3000 register space. Immediately after reset, these four bytes are loaded with the factory- programmed values in the OTP memory. For a standard device, these values are all zeroes. Unique serial numbers or other information could be stored here.
Page 37: Write Protect Logic
SH3000 User Manual Preliminary 8.2 Write Protect Logic The SH3000 MicroBuddy™ provides a comprehensive set of write-protect flags to safeguard groups of related bits from inadvertent corruption. Register WP_PostScale (R0x17) contains four write-protect flags, each acting on one group of bits.
Page 38 SH3000 User Manual Preliminary Write Protect Logic Registers RESET RESET EVENT VALUE NAME DESCRIPTION XTALtune Rewrite-Once Enable (see notes for use) P W B 0 b6 Register Page for R0x10 through R0x17. 0 =Page0, 1 =Page1. P W B 0 b5 ForceDCOon. Forces HF Oscillator to run under all conditions.
Page 39: Voltage Regulator
Using V to drive external loads may degrade the performance of the SH3000. 8.4 Backup Power The V pin can be connected to a backup power supply for the real-time clock, +2.3 to +5.5 V (+1.8 to +5.5 V typical).
Page 40: Registers
SH3000 User Manual Preliminary 9. Registers Table 7: SH3000 MicroBuddy™ Registers 0x00 to 0x0F Timer, RTC, Configuration, and Control Registers RESET RESET EVENT VALUE NAME DESCRIPTION 0x00 PeriodMSB W B 0x00 Periodic Interrupt / Wake-up Timer setting. 0x01 Period2 W B 0x00 With 32.768 kHz clock the period = (32-bit value)/32768.
Page 41: Table 8: Sh3000 Microbuddy™ Registers 0X10 To 0X17
SH3000 User Manual Preliminary Table 8: SH3000 MicroBuddy™ Registers 0x10 to 0x17 Control, Setting, and Calibration Registers Initialized from OTP Memory INIT INIT WRITE EVENT VALUE PROTECT NAME DESCRIPTION Reserved, not used Reserved, not used 0x10 Value 0x?? Threshold Value, 2.3 V to 4.4 V in ~33.33 mV steps.
Page 42 SH3000 User Manual Preliminary Control, Setting, and Calibration Registers Initialized from OTP Memory (continued) INIT INIT WRITE EVENT VALUE PROTECT NAME DESCRIPTION P W B Amount of HFCLK Spectrum Spreading, 4 (four) settings. P W B P W B EnableSS, enable spectrum spreading.
Page 43: Table 9: Sh3000 Microbuddy™ Registers 0X18 To 0X1F
SH3000 User Manual Preliminary Table 9: SH3000 MicroBuddy™ Registers 0x18 to 0x1F Control and Status Registers RESET RESET EVENT VALUE NAME DESCRIPTION b7 Reserved, not used P W B 1 b6 P W B 0 b5 P W B 0 b4...

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