Cpu Supervisor Registers - Semtech SH3000 User Manual

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2.3 CPU Supervisor Registers

NAME
0x0E
Config
NAME
0x10
0 V
Value
BO
0x17
0 WP_PostScale
SH3000UM version 0.95
Copyright ©2002 Semtech Corporation
RESET
RESET
EVENT
VALUE
P
1
b7 XTALtune Rewrite-Once Enable (see notes for use)
P W B
0 b6 Register Page for R0x10 through R0x17. 0 =Page0, 1 =Page1.
P W B
0 b5 ForceDCOon. Forces HF Oscillator to run under all conditions.
P W B
0 b4 CLK
0x88
P W B
1 b3 CLK
P W B
0 b2 WdogClkSelect. 1 = CLK
P W B
0 b1 Interrupt Flag Clear. 1 = clear, 0 = no effect, always reads 0.
P W B
0 b0 Interrupt Enable. 1 = enable, 0 = disable.
INIT
INIT
WRITE
EVENT
VALUE
PROTECT
-0-
-0-
P W
?
P W
?
0x??
P W
?
P W
?
P W
?
P W
?
P W
?
P W
?
P W
?
P W
?
0x??
P W B
?
P W B
?
P W B
?
P W B
?
2002-08
DESCRIPTION
source. 1 = 32 kHz, 0 = HFCLK.
OUT
Enable. 1 = enable, 0 = disable.
OUT
, 0 = 32 kHz.
OUT
DESCRIPTION
b7
Reserved, not used
b6
Reserved, not used
V
b5
V
b4
V
b3
V
Threshold Value, 2.3 V to 4.4 V in
BO
~33.33 mV steps.
V
b2
V
b1
V
b0
b7
IDCode Write Protect, 1 = no writes.
b6
Calibration Write Protect, 1 = no writes.
Application Write Protect, 1 = no writes.
b5
b4
V
Value Write Protect, 1 = no writes.
BO
A
b3
CLK32 enable, 1 = enable, 0 = disable.
A
b2
DCO Post-Scaler, 8 (eight) setting:
A
b1
/1, 2, 4, 8, 16, 32, 64, 128.
A
b0
SH3000 User Manual
Preliminary
8

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