Table 3: Operating Parameters For Fll - Semtech SH3000 User Manual

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For example, a post-divider setting of /8 and the Frequency Set value of 4000 (0x0FA0) produce an output

frequency of 1.024 MHz. Table 3 shows the available frequencies with the corresponding resolution at

high and low frequency limits.

When the Frequency Set value changes, the FLL synthesizer needs some settling time to lock the new

frequency. There are several possible methods for decreasing this time:

1. The host microcontroller may simply wait for the FLL to lock, checking the FLL lock flag (bit 0) in

the Status register (R0x1A). This approach is the simplest but also the slowest. Depending on

the frequency step it may take up to two seconds to obtain the lock. The frequency change from

the old to the new value is slow and gradual.

2. The host may issue a Coarse Lock command by setting the coarse lock bit (bit 1) in the

FLLcontrol register (R0x0F). The SH3000 performs a successive approximation algorithm on

the 18-bit DCO (digitally controlled oscillator) code value (contained in registers R0x13, R0x14,

and R0x18) and finds a locked setting in approximately 25 ms. The clock may experience

frequency fluctuations of up to 2:1.

3. If the frequency step is small (less than 256 kHz at the undivided output of the HF oscillator), the

host may issue a fine lock command by setting the fine lock bit (bit 2) in the FLLcontrol register.

The SH3000 performs a successive approximation algorithm on the 7 least significant bits of the

18-bit DCO code value, and finds a locked setting in approximately 5 ms. The clock may

experience the maximum frequency fluctuations of only 3.2%.

4. The host may write the new value into the DCO code registers to directly control the frequency of

the HF oscillator. This method is preferable and results in minimum settling time. The 18-bit

DCO code value can be obtained from programming the HF oscillator to a correct frequency using

method 2 or 3 above (at start-up or at some point in the operation), reading the value from the

DCO code registers, and storing the value in the host's memory. This calibration should be

performed for each of the frequencies to be employed. This method allows the locking time to be

as small as 1 or 2 ms, independent of the frequency step.

SH3000UM version 0.95