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Pin
Name
Type
1
Power
V
SS
2
V
Power
REG
3
V
Power
DD
4
V
Power
BAK
5
X
Analog In
IN
6
X
Analog Out
OUT
7
CLK
Digital In
SEL
8
V
Power
SS
9
R
Analog
REF
10
RST
Digital Out
N
11
RST
Digital Out
12 T
(V
)
Digital In
EST
SS
13
CLK32
Digital Out
14
I/O
IO/I
NT
15
CLK
Digital In
IN
16
CLK
Digital Out
OUT
SH3000UM version 0.95
Copyright ©2002 Semtech Corporation
Table 1: SH3000 MicroBuddy™ Pin Descriptions
Ground, 0 V. All V
SS
Output of internal voltage regulator, 2.2 V nominal. This pin can power external
loads of <5 mA. If load is "noisy," it requires a bypass capacitor. May be left
unconnected or used as a high logic level signal for CLK
Main power supply, +2.3 to +5.5 V.
Backup power supply for real-time clock, +2.3 to +5.5 V (+1.8 to +5.5 V typical).
This voltage can be higher or lower than V
capacitor (with external recharge circuit). Connect to V
Oscillator pins for an optional external low-frequency crystal, typically a 32.768 kHz
watch crystal with nominal 12.5 pF load capacitance. Keep open or connect to V
if not used.
A logic low level selects the internal 32 kHz RC oscillator (CLK
high state on this pin selects the 32 kHz crystal oscillator (CLK
V
). The SH3000 always starts up using the internal 32 kHz RC oscillator. If
REG
CLK
is high, the internal 32 kHz clock switches to the crystal oscillator once it
SEL
has stabilized, and RC oscillator is disabled for power conservation.
Do not connect CLK
SEL
left open.
Ground, 0 V. All V
SS
Optional 1 MOhm external bias resistor for the internal 32 kHz RC oscillator. Can
be used to set, trim or modulate the internal RC oscillator. Keep open if not used.
Active low system reset output. Asserted with a strong low state when a reset
condition occurs. Weakly pulled to V
valid for V
as low as 1 V. Keep open if not used.
DD
Active high system reset output. Asserted with a strong high state when a reset
condition occurs. Weakly pulled to V
valid for V
as low as 1 V. Keep open if not used.
DD
Factory test enable. All V
Buffered internal 32 kHz clock, derived according to the CLK
uses backup power for the buffer when V
signal is either at V
BAK
enabled, this signal runs continuously independent of CLK
external load to reduce power consumption during backup operations. When
disabled, this pin is driven to V
Serial communications interface and interrupt output pin. This pin is internally
weakly pulled to the opposite of the programmed interrupt polarity. For example, if
interrupt is programmed to be active low, this pin is weakly pulled to V
inactive. Keep open if not used.
Clock activity sense input. Used to detect when the target microcontroller enters
stop mode (which disables its clock). Connect to the microcontroller's clock output
or oscillator output pin. Connect to V
open.
Programmable high-frequency clock output. Connect to the target microcontroller's
clock input or oscillator input pin. Keep open if not used.
2002-08
Function
pins and T
(V
) pin must be connected together.
EST
SS
. Connect a backup battery or backup
DD
to any signals except V
pins and T
(V
) pin must be connected together.
EST
SS
internally when not active. This signal is
DD
internally when not active. This signal is
SS
pins and T
(V
SS
EST
SS
is not present. When driving high, this
DD
or V
(if V
is higher than the reset threshold). When
DD
DD
. Keep open if not used.
SS
when not used. CLK
SS
SH3000 User Manual
Preliminary
pin (see below).
SEL
if not used.
DD
tied to V
SEL
is connected to
SEL
or V
. CLK
must not be
SS
REG
SEL
) pin must be connected together.
pin setting. This pin
SEL
activity. Minimize the
OUT
DD
must not be left
IN
3
SS
). A
SS
when
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