Epson S5U13A05B00C User Manual
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Epson S5U13A05B00C User Manual

Epson S5U13A05B00C User Manual

S1d13a05 lcd/usb companion chip
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S1D13A05 LCD/USB Companion Chip
S5U13A05B00C Rev. 1.0
Evaluation Board User Manual
Document Number: X40A-G-004-02.1
Rev. 1.1

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Summary of Contents for Epson S5U13A05B00C

  • Page 1 S1D13A05 LCD/USB Companion Chip S5U13A05B00C Rev. 1.0 Evaluation Board User Manual Document Number: X40A-G-004-02.1 Rev. 1.1...
  • Page 2 This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any kind of damage and/or fire caused by the use of it.

  • Page 3: Table Of Contents

    12 Sales and Technical Support ......35 Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...
  • Page 4 THIS PAGE LEFT BLANK Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...

  • Page 5: Introduction

    Introduction 1 Introduction This manual describes the setup and operation of the S5U13A05B00C Rev. 1.0 Evaluation Board. The board is designed as an evaluation platform for the S1D13A05 LCD/USB Companion Chip. This document is updated as appropriate. Please check for the latest revision of this document before beginning any development.

  • Page 6: Features

    • Direct interface for 18-bit TFT Type 2 LCD panel support • Direct interface for 18-bit TFT Type 3 LCD panel support • Direct interface for 18-bit TFT Type 4 (Epson ND-TFD) LCD panel support. • Programmable clock synthesizer to CLKI and CLKI2 for maximum clock flexibility.

  • Page 7: Installation And Configuration

    3 Installation and Configuration The S5U13A05B00C is designed to support as many platforms as possible. The S5U13A05B00C incorporates a DIP switch and five jumpers which allow both the evalu- ation board and the S1D13A05 LCD controller to be configured for a specified evaluation platform.
  • Page 8 CLKI to BCLK Divide ratio 2:1 CLKI to BCLK divide ratio 1:1 SW1-8 Disable PCI bridge for non-PCI host Enable PCI bridge for PCI host = Required settings when using the PCI Bridge FPGA Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...

  • Page 9: Configuration Jumpers

    Installation and Configuration 3.2 Configuration Jumpers The S5U13A05B00C has five jumper blocks which configure various setting on the board. The jumper positions for each function are shown below. Table 3-2: Jumper Summary Jumper Function Position 1-2 Position 2-3 No Jumper...
  • Page 10 (default setting). When the jumper is at position 2-3, the CLKI2 source is the external oscillator at U7. MCLKOUT from External clock synthesizer oscillator (U7) Figure 3-3: Configuration Jumper (JP2) Location Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...
  • Page 11 When the jumper is at position 1-2, the USB IRQ on PCI is enabled (default setting). When no jumper is installed, the USB IRQ on PCI is disabled. USB IRQ USB IRQ on PCI disabled on PCI enabled Figure 3-5: Configuration Jumper (JP4) Location Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...
  • Page 12 H3. When no jumper is installed, GPO0 is not sent to H3. GPIO0 not Inverted Normal sent to H1 (Active Low) (Active High) Figure 3-6: Configuration Jumper (JP5) Location Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...

  • Page 13: Cpu Interface

    If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16]. These pins are not used in their corresponding host interface mode. Systems are responsible for externally connecting them to IO V Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...

  • Page 14: Cpu Bus Connector Pin Mapping

    Connected to WE0# of the S1D13A05 Connected to WAIT# of the S1D13A05 Connected to CS# of the S1D13A05 Connected to MR# of the S1D13A05 Connected to WE1# of the S1D13A05 Connected to +3.3V Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...
  • Page 15 +5 volt supply Connected to RD/WR# of the S1D13A05 Connected to BS# of the S1D13A05 Connected to BUSCLK of the S1D13A05 Connected to RD# of the S1D13A05 Not connected Not connected Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...

  • Page 16: Lcd Interface Pin Mapping

    FPSHIFT. For further FPDATxx to LCD interface mapping, see S1D13A05 Hardware Functional Specification, document number X40A-A-001-xx. GPO0 can be inverted on H1 by setting JP5 to 2-3. Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...
  • Page 17 GPO1 GPO2 XOEV GPO2 GPO3 GPO3 GPO4 PCLK1 GPO4 GPO5 PCLK2 GPO5 GPO6 XRESH GPO6 GPO7 XRESV GPO7 GPO8 XOHV GPO8 GPO9 XSTBY GPO9 GPO10 PMDE GPO10 2-26 Even Numbers Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...

  • Page 18: Technical Description

    PCI Bridge FPGA to support the PCI bus. 6.2 Direct Host Bus Interface Support The S5U13A05B00C is specifically designed to work using the PCI Bridge FPGA in a standard PCI bus environment. However, the S1D13A05 directly supports many other host bus interfaces.

  • Page 19: Adjustable Lcd Panel Positive Power Supply

    +23V and +40V (I =45mA). Such a power supply (VDDH) has been provided on the S5U13A05B00C board. VDDH can be adjusted using R14 to provide an output voltage from +23V to +40V, and is enabled/disabled using the S1D13A05 general purpose signal, GPO0 (active high).

  • Page 20: Extended Lcd Connector

    The S1D13A05 USB controller provides a Revision 1.1 compliant USB client. The S1D13A05 acts as a USB device and connects to an upstream hub or USB host through connector J1 on the S5U13A05B00C evaluation board. Clamping diodes have been added to protect the USB bus from ESD and shorting.
  • Page 21 If an oscillator or another type of clock external source is used, USBOCSI needs to be disabled by using a pull- down resistor and disabling or removing the crystal oscillator circuitry. Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...

  • Page 22: Clock Synthesizer And Clock Options

    Clock Synthesizer and Clock Options 7 Clock Synthesizer and Clock Options For maximum flexibility, the S5U13A05B00C implements a Cypress ICD2061A Clock Synthesizer. MCLKOUT from the clock synthesizer is connected to CLKI2 of the S1D13A05 and VCLKOUT from the clock synthesizer is connected to CLKI of the S1D13A05.

  • Page 23: Parts List

    3x1, 0.1” pitch unshrouded JP1,JP2,JP3,JP5 HEADER 3 header 2x1, 0.1” pitch unshrouded Do not purchase or populate JP4,JP6 HEADER 2 header JP6. USB B Right Angle, Type B USB AMP 787780-1 Connector Connector Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...
  • Page 24 Epson R&D. 5V fixed voltage regulator, Linear Technology LT1117CST- LT1117CST-5 SOT-223 TI74AHC04, equivalent 74AHC04 Inverter, SO-14 package (Fairchild, 74VHC04SJ) Clock chip generator, wide SO- ICD2061A Cypress ICD2061A 16 package Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...
  • Page 25 PCI bracket with slot for USB PCI bracket (Same bracket used for Type B conn 13A03B00B board) Pan Head use to assemble PCI bracket Screw, pan head, #4-40 x 1/4” Screw onto board Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...

  • Page 26: Schematics

    Schematics 9 Schematics Figure 9-1: S1D13A05B00C Schematics (1 of 6) Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...
  • Page 27 Schematics Figure 9-2: S1D13A05B00C Schematics (2 of 6) Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...
  • Page 28 Schematics Figure 9-3: S1D13A05B00C Schematics (3 of 6) Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...
  • Page 29 Schematics Figure 9-4: S1D13A05B00C Schematics (4 of 6) Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...
  • Page 30 Schematics Figure 9-5: S1D13A05B00C Schematics (5 of 6) Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...
  • Page 31 Schematics Figure 9-6: S1D13A05B00C Schematics (6 of 6) Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...

  • Page 32: Board Layout

    Board Layout 10 Board Layout Figure 10-1: S5U13A05B00C Board Layout (Top View) Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...
  • Page 33 Board Layout Figure 10-2: S5U13A05B00C Board Layout (Bottom View) Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...

  • Page 34: Change Record

    Change Record 11 Change Record X40A-G-004-02 Revision 1.1 - Issued: March 28, 2018 • updated Sales and Technical Support Section • updated some formatting Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board Rev. 1.1...

  • Page 35: Sales And Technical Support

    Sales and Technical Support 12 Sales and Technical Support For more information on Epson Display Controllers, visit the Epson Global website. https://global.epson.com/products_and_drivers/semicon/products/display_controllers/ For Sales and Technical Support, contact the Epson representative for your region. https://global.epson.com/products_and_drivers/semicon/information/support.html Seiko Epson Corporation S5U13A05B00C Rev 1.0 Evaluation Board...

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