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Installation and Configuration
All S1D13A05 configuration inputs are fully configurable using the eight position DIP
switch as described below.
Switch
S1D13A05
(SW1)
Signal
SW1-5,
CNF4,
SW1-[3:1]
CNF[2:0]
SW1-4
CNF3
SW1-6
CNF5
SW1-7
CNF6
SW1-8
-
= Required settings when using the PCI Bridge FPGA
8
All manuals and user guides at all-guides.com
Table 3-1: Configuration DIP Switch Settings
Value on this pin at rising edge of RESET# is used to configure:
Closed (On/1)
Select host bus interface as follows:
CNF4 CNF2
CNF1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
1
1
0
1
0
0
1
1
1
0
0
1
0
1
1
0
0
1
0
1
1
1
0
1
1
X
1
1
Reserved. Must be set to 1.
WAIT# is active high
CLKI to BCLK Divide ratio 2:1
Disable PCI bridge for non-PCI host
Seiko Epson Corporation
CNF0
Host Bus Interface
0
SH-4/SH-3 interface, Big Endian
0
SH-4/SH-3 interface, Little Endian
1
MC68K #1, Big Endian
1
Reserved
0
MC68K #2, Big Endian
0
Reserved
1
Generic #1, Big Endian
1
Generic #1, Little Endian
0
Reserved
0
Generic #2, Little Endian
1
RedCap 2, Big Endian
1
Reserved
0
DragonBall, Big Endian
0
Reserved
1
Reserved
WAIT# is active low
CLKI to BCLK divide ratio 1:1
Enable PCI bridge for PCI host
Open (Off/0)
S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1
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