Interfacing Drv8316Revm And Launchxl-F280049C Launchpad - Texas Instruments DRV8316REVM User Manual

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Hardware and Software Overview
Table 4-4. User-Adjustable Resistor Divider Settings for DRV8316T Variant (defaults in bold) (continued)
Setting
Name
SLEW
Slew rate
OCP/SR
Overcurrent
Protection / Smart
Rectification
GAIN
G
CSA

4.4 Interfacing DRV8316REVM and LAUNCHXL-F280049C LaunchPad

The DRV8316REVM has 40 pins with different functions. These pins are interfaced with the LAUNCHXL-
F280049C LaunchPad development kit and are mapped appropriately to receive the functionalities of the
DRV8316R device. These 40 pins are grouped into 4 ports in respect to the LAUNCHXL-F280049C (J1 to J4).
Table 4-5
and
Table 4-6
list the interfacing of these ports of the DRV8316REVM headers J3 and J4.
Table 4-5. Connections for Header J3 on DRV8316REVM (DNP in bold)
J3 Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
12
DRV8316REVM Evaluation Module
Description
Phase pin slew rate switching low
to high (10-90%) and high to low
(90-10%)
Selects the Mode for Overcurrent
and Smart Rectification Settings
(ASR = Automatic Synchronous
Rectification; AAR = Automatic
Asynchronous Rectification)
Current sense gain
DRV8316REVM
LAUNCHXL-F280049C
Function
Function
3.3VBK (DNP)
3.3 V
Not used
5 V
Not used
PGA1/3/5_GND
AGND
GND
Not used
GPIO13/SCIBRX
VSENA
ADCINA5
Not used
GPIO40/SCIBTX
VSENB
ADCINB0
nSLEEP (DNP)
NC
VSENC
ADCINC2
Not used
ADCINB3/VDAC
VSENVM
ADCINB1
SCLK
SPIACLK
ISENA
ADCINB2
Copyright © 2021 Texas Instruments Incorporated
Resistors
Hardware
(AVDD/ AGND)
R38/R43
Tied to AGND
Hi-Z
47 kΩ to AVDD
Tied to AVDD
R41/R46
Tied to AGND
22 kΩ to AGND
100 kΩ to AGND
Hi-Z
100 kΩ to AVDD
22 kΩ to AVDD
Tied to AVDD
R39/R44
Tied to AGND
Hi-Z
47 kΩ to AVDD
Tied to AVDD
Description
3.3-V LaunchPad supply
5-V LaunchPad supply
Not used
GND connection
Not used
Phase A Voltage Sense
Not used
Phase B voltage sense
For internal use only
Phase C voltage sense
Not used
VM Bus voltage sense
SPI clock (DRV8316R only)
Phase A current sense
SLVUBZ9A – DECEMBER 2020 – REVISED FEBRUARY 2021
www.ti.com
Setting
25 V/µs
50 V/µs
125 V/µs
200 V/µs
OCP = 10 A
ASR and AAR
Disabled
OCP = 15 A
ASR and AAR
Disabled
OCP = 10 A
ASR Enabled
OCP = 10 A
ASR and AAR
Enabled
OCP = 15 A
ASR Enabled
OCP = 15 A
ASR and AAR
Enabled
OCP = 15 A
ASR and AAR
Enabled
0.15 V/A
0.3 V/A
0.6 V/A
1.2 V/A
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