Figure 7.4. J7/J8 Header Landing Control; Figure 7.5. J9/J10 Header Landing Control - Lattice Semiconductor MachXO2280 Breakout Board User Manual

MachXO 2280 Breakout Board Evaluation Kit
Evaluation Board User Guide
J9
1
2
VCC_3.3 V
GND
VCC_3.3 V
GND
VCC_3.3 V
GND
NC
GND
NC
VCC_CORE
D7
GND
A9
GND
N9
GND
M9
GND
NC
NC
NC
NC
P13
GND
R14
GND
T14
GND
T15
GND
P14
GND
R15
GND
R16
GND
P15
GND
P16
GND
39
40
© 2011-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
24

Figure 7.4. J7/J8 Header Landing Control

J10
1
2
P8
P2
P7
P3
N8 N5
P9
N6
P10
T2
M10
T3
R9 R4
R10
R5
T10
P5
T11 P6
N10
T5
N11
T4
R11
R6
R12 T6
P11
T8
P12
T7
T13
M7
T12 M8
R13
R7
NC
R8
39
40

Figure 7.5. J9/J10 Header Landing Control

J8
1 2
D14 H16
D13
J16
GND
GND
E13
J15
E12
K15
GND GND
E14
J13
F14
K13
GND
GND
C15
L15
D15
M15
GND GND
E14 L14
F15
M14
GND
GND
G12
N15
G13
N14
GND GND
G14 N13
H14 N12
39
40
Top Side
J9 J10
J7
1 2
F13 GND
F12 GND
B16
GND
C16
GND
D16
GND
E16 GND
F16 GND
G16 GND
H12
GND
H13
GND
G15
GND
H15 GND
NC M16
NC N16
J12
L12
K12
L13
J14
M12
K14
M13
K16 L11
L16 M11
39 40
FPGA-EB-02038-1.2