Evaluation Board Hardware; Device Description; Hardware Link Options - Analog Devices EVAL-AD7175-2SDZ User Manual

UG-AD7175-2

EVALUATION BOARD HARDWARE

DEVICE DESCRIPTION

The AD7175-2 is a highly accurate, high resolution, multiplexed,
2-/4-channel (fully differential/single-ended) Σ-Δ ADC. The
AD7175-2 has a maximum channel-to-channel scan rate of
50 kSPS (20 µs) for fully settled data The output data rates range
from 5 SPS to 250 kSPS. The device includes integrated rail to
rail analog input and reference input buffers, an integrated
precision 2.5 V reference, and an integrated oscillator.
See the AD7175-2 data sheet for complete specifications.
Consult the data sheet in conjunction with this user guide when
Table 1. Default Link and Solder Link Options
Link Default Option
LK1 A
LK2 B
LK5 to LK9 Inserted
SL1 A
SL2 A
SL3 A
SL4 A
SL5 B
SL8 A
SL9 A
SL10 A
SL11 A
R49 to R51 Inserted
Description
Selects the voltage applied to the power supply sequencer circuit (U3); dependent on AVDD1. Place in
Position A if using 5 V AVDD1, or Position B if using 2.5 V AVDD1.
Selects the external power supply from Connector J3 (Position A), or J4 (Position B).
Inserting these links sets up the on-board noise test. In this mode, all inputs short to the common
voltage via SL11.
Sets the voltage applied to the AVDD2 pin. Operates using the AVDD1 supply (default). Position B sets
the AVDD2 voltage to 3.3 V supply from the
Selects between an external or on-board AVDD1 source. Supplies AVDD1 from the
(default).
Selects between an external or on-board AVSS source. Supplies AVSS from the
Connects AIN4 to: A4 / J6 (Position A), REFOUT pin on the
Positions B and C are used to simplify using a single ended input source.
Selects between an external or on-board IOVDD source. Supplies IOVDD from the
(default). The evaluation board operates with a 3.3 V logic.
Routes A0 to: AIN0 pin on the
gain of 0.8x (Position C) or J10-1 (Position D).
Routes A2 to: AIN2 pin on the
0.4x (Position C).
Routes A3 to: AIN3 pin on the
0.4x (Position C).
Routes A1 to: AIN1 pin on the
gain of 0.8x (Position C) or J10-7 (Position D).
Connects AVSS and AGND for single-supply operation. To operate in split supply mode, remove these links.
Rev. Pr.C | Page 4 of 12
EVAL-AD7175-2SDZ User Guide
using the evaluation board. Full details for the
are available on the Analog Devices website.

HARDWARE LINK OPTIONS

See Table 1 for default link options. By default, the board is
configured to operate from the supplied 9 V ac-to-dc adapter
connected to connector J5. The 5 V supply required for the
AD7175-2 comes from the on-board low dropout regulator
(LDO). The ADP7118, with a 5 V output voltage, receives its
input voltage from J3 or J5 (depending on the position of LK2)
and generates a 5 V output.
ADP7118 (3.3 V) (U10) regulator.
AD7175-2
AD7175-2 (Position A), Buffer/Inamp U8 (Position B), Funnel Amp U9 with
AD7175-2 (Position A), Buffer U12 (Position B) or Funnel Amp U9 gain of
AD7175-2 (Position A), Buffer U12 (Position B) or Funnel Amp U9 gain of
AD7175-2 (Position A), Buffer/Inamp U8 (Position B), Funnel Amp U9 with
EVAL-SDP-CB1Z
ADP7118 (5 V) (U7)
ADP7182 (-2.5 V) (U4) (default).
(Position B) or AVSS (Position C).
ADP7118 (3.3 V) (U10)