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PCH 6/9
5
C1390
6-22-24R00-1B9
12p_50V_NPO_04
6-22-24R00-1BA
D02 0714
_
FSX3M
R1760
D02 0714
1M_1%_04
X6
C1392
_
12p_50V_NPO_04
D
FSX3M_24MHZ
_
_
RTC (10M OHM RES): DO NOT CHANGE TO 0402
C1391
12p_50V_04
_
X5
R1765
10M_06
1TJS125DJ4A420P
_
D02 0707
CM200S
C1389
12p_50V_04
_
32.768KHZ
_
6-22-32R76-0B2
6-22-32R76-0BJ
3.3VS
C
R2179
*10K_1%_04
TBT_CLKREQ_N
TBT_CLKREQ_N
R2180
X
*10K_1%_04
X
3.3VS
RN7
10K_8P4R_04
1
8
SSD_CLKREQ#
W LAN_CLKREQ#
2
7
3
6
PEG_CLKREQ#
4
5
LAN_CLKREQ#
R1761
*10K_04
PEG_CLKREQ#
Any used, enable, and mapped SRCCLKREQ# signal
should connect to a PCIE* connector pin or
B
a device down ball with 10K ohm external pull-up resistor to core rail.
SRCCLKREQ#[7:0] signal can be mapped to any of the CLKOUT_PCIE_P/N[7:0]
SRCCLKREQ#[15:8] signal can be mapped to any of the CLKOUT_PCIE_P/N[15:8]
PCIE CLK
SRCCLKREQ#
Usage
GLAN
5
5
WLAN
6
6
9
SSD (x4 LANE)
9
10
PEG (x8)
10
A
5
4
3
SPT-H_PCH
U138G
AR17
GPP_A16/CLKOUT_48
G1
X
[5]
CPU_24MHZ_R_DP
CLKOUT_CPUNSSC_P
F1
[5]
CPU_24MHZ_R_DN
CLKOUT_CPUNSSC
100 MHz
CLKOUT_CPUPCIBCLK
G2
[5]
PCH_CPU_BCLK_R_DP
CLKOUT_CPUBCLK_P
CLKOUT_CPUPCIBCLK_P
H2
[5]
PCH_CPU_BCLK_R_DN
CLKOUT_CPUBCLK
A5
XTAL24_OUT
A6
XTAL24_IN
R1764
2.7K_1%_04
XCLK_RBIAS
E1
VDD1.0
XCLK_BIASREF
RTC_X1
_
BC9
RTCX1
RTC_X2
BD10
RTCX2
BC24
GPP_B5/SRCCLKREQ0#
AW24
GPP_B6/SRCCLKREQ1#
AT24
[34]
TBT_CLKREQ_N
GPP_B7/SRCCLKREQ2#
BD25
GPP_B8/SRCCLKREQ3#
BB24
GPP_B9/SRCCLKREQ4#
LAN_CLKREQ#
BE25
[38]
LAN_CLKREQ#
GPP_B10/SRCCLKREQ5#
AT33
[42]
W LAN_CLKREQ#
GPP_H0/SRCCLKREQ6#
AR31
GPP_H1/SRCCLKREQ7#
BD32
GPP_H2/SRCCLKREQ8#
BC32
[43]
SSD_CLKREQ#
GPP_H3/SRCCLKREQ9#
PEG_CLKREQ#
BB31
[19]
PEG_CLKREQ#
GPP_H4/SRCCLKREQ10#
BC33
GPP_H5/SRCCLKREQ11#
BA33
GPP_H6/SRCCLKREQ12#
AW33
GPP_H7/SRCCLKREQ13#
BB33
GPP_H8/SRCCLKREQ14#
BD33
GPP_H9/SRCCLKREQ15#
R13
CLKOUT_PCIE_N15
R11
CLKOUT_PCIE_P15
P1
CLKOUT_PCIE_N14
R2
CLKOUT_PCIE_P14
W7
CLKOUT_PCIE_N13
Y5
CLKOUT_PCIE_P13
U2
CLKOUT_PCIE_N12
U3
CLKOUT_PCIE_P12
HM170
7 OF 12
_
intel
GPIO power rail PU SUS well
SRCCLKREQ#
PU core rail
S3
[9,10,11,12,14,25,27,28,29,31,33,35,38,39,40,41,42,43,44,47,49,51,53]
4
3
2
L1
PCH_XDP_CLK_DN
CLKOUT_ITPXDP
L2
PCH_XDP_CLK_DP
CLKOUT_ITPXDP_P
X
J1
X
PCH_CPU_PCIBCLK_R_DN
[5]
100 MHz
J2
PCH_CPU_PCIBCLK_R_DP
[5]
N7
CLKOUT_PCIE_N0
N8
CLKOUT_PCIE_P0
L7
CLKOUT_PCIE_N1
L5
CLKOUT_PCIE_P1
D3
CLKOUT_PCIE_N2
TBT_REFCLK_100_N
[34]
F2
TBT_REFCLK_100_P
[34]
CLKOUT_PCIE_P2
E5
CLKOUT_PCIE_N3
G4
CLKOUT_PCIE_P3
D5
CLKOUT_PCIE_N4
E6
CLKOUT_PCIE_P4
D8
CLKOUT_PCIE_N5
CLK_PCIE_GLAN#
[38]
D7
CLK_PCIE_GLAN
[38]
CLKOUT_PCIE_P5
R8
CLKOUT_PCIE_N6
CLK_PCIE_MINI#
[42]
R7
CLKOUT_PCIE_P6
CLK_PCIE_MINI
[42]
U5
CLKOUT_PCIE_N7
U7
CLKOUT_PCIE_P7
W10
CLKOUT_PCIE_N8
W11
CLKOUT_PCIE_P8
N3
CLKOUT_PCIE_N9
CLK_PCIE_SSD#
[43]
N2
CLK_PCIE_SSD
[43]
CLKOUT_PCIE_P9
P3
CLKOUT_PCIE_N10
VGA_PEXCLK#
[19]
P2
VGA_PEXCLK
[19]
CLKOUT_PCIE_P10
R3
CLKOUT_PCIE_N11
R4
CLKOUT_PCIE_P11
REV = 1.3
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
[31,47,48]
VDD1.0
3.3VS
Title
Title
Title
[30] PCH 7/12-CLKOUT
[30] PCH 7/12-CLKOUT
[30] PCH 7/12-CLKOUT
Size
Size
Size
Document Number
Document Number
Document Number
6-7P-N15F9-003
6-7P-N15F9-003
6-7P-N15F9-003
A3
A3
A3
Date:
Date:
Date:
Thursday, March 17, 2016
Thursday, March 17, 2016
Thursday, March 17, 2016
2
Schematic Diagrams
1
D
Sheet 30 of 62
PCH 6/9
C
B
A
Rev
Rev
Rev
1.0
1.0
1.0
Sheet
Sheet
Sheet
30
30
30
of
of
of
66
66
66
1
PCH 6/9 B - 31
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