Processor 4/7 - Clevo N170RD1 Service Manual

Schematic Diagrams

Processor 4/7

D
Sheet 5 of 62
C
Processor 4/7
B
[12,25,40,49,51]
A
[40] H_PROCHOT_EC
B - 6 Processor 4/7
5 4
Processor 4/7 ( CLK/JTAG/MISC )
NEAR CPU
1.0V_VCCST
R1347 R1348
100_04 56.2_1%_04
[30]
[30]
_ _
[49,51] H_CPU_SVIDDAT
[49,51] H_CPU_SVIDALRT#
[49,51] H_CPU_SVIDCLK
R1357
220_04
_
H_PROCHOT#
R1366
[49,51,56] H_PROCHOT#
[46] DDR_VTT_PG_CTRL
VCCST_PWRGD
R1369 60.4_1%_04
_
H_PM_DOWN_R
R1371 20_1%_04
[27] H_PM_DOWN
R1373
[27] PCH_PECI
R1375
_
[40] H_PECI
[27] PCH_THERMTRIP#
[29]
VCCST_PWRGD 1.0V_VCCST
R1382
VDD3
1K_04
VCCST_PWRGD
_
R1383
100K_04
D
C956
_
5 G
*0.01u_16V_X7R_04
S Q71B
X
MTDK3S6R
D
_
R2019 0_04 2 G
ALL_SYS_PWRGD
S Q71A
C1832
_ MTDK3S6R
_
*0.1u_10V_X5R_04
X
1.0DX_VCCSTG
H_PROCHOT# R1384 1K_04
_
Q62
G
C957
MTN7002ZHS3
47P_50V_NPO_04
_
R1385
_
100K_04
_
CAD Note: Capacitor need to be placed
close to buffer output pin
5 4
3
SKYLAKE_HALO
U137E
BGA1440
B31 BN25
[30] PCH_CPU_BCLK_R_DP BCLKP CFG[0]
A32 BN27
[30] PCH_CPU_BCLK_R_DN
BCLKN CFG[1]
BN26
CFG[2]
D35 BN28
PCH_CPU_PCIBCLK_R_DP PCI_BCLKP CFG[3]
C36 BR20
PCH_CPU_PCIBCLK_R_DN
PCI_BCLKN CFG[4]
BM20
CFG[5]
E31 BT20
[30] CPU_24MHZ_R_DP CLK24P CFG[6]
D31 BP20
[30] CPU_24MHZ_R_DN
CLK24N CFG[7]
BR23
CFG[8]
BR22
CFG[9]
BT23
CFG[10]
BT22
CFG[11]
BM19
CFG[12]
BR19
CFG[13]
BP19
CFG[14]
CPU_VIDALERT# BH31 BT19
VIDALERT# CFG[15]
BH32
VIDSCK
BH29 BN23
H_PROCHOT#_R VIDSOUT CFG[17]
499_1%_04 BR30 BP23
PROCHOT# CFG[16]
BP22
CFG[19]
BT13 BN22
_
DDR_VTT_CNTL CFG[18]
BR27
BPM#[0]
BT27
BPM#[1]
BM31
BPM#[2]
VCCST_PWRGD_CPU H13 BT30
VCCST_PWRGD BPM#[3]
BT31
[28] H_PWRGD
PROCPWRGD
BP35 BT28
[27] PLTRST_CPU_N
RESET# PROC_TDO
BM34 BL32
[27] H_PM_SYNC PM_SYNC PROC_TDI
BP31 BP28
PM_DOWN PROC_TMS
H_PECI_R BT34 BR28
*12.1_1%_04
PECI PROC_TCK
*20mil_short_04 J31
THERMTRIP#
X BP30
PROC_TRST#
H_SKTOCC# BR33 BL30
X
H_SKTOCC#
SKTOCC# PROC_PREQ#
BN1 BP27
PROC_SELECT# PROC_PRDY#
BM30
CATERR#
11/9 remove BT25
CFG_RCOMP
5 OF 14
SKL_H_BGA_BGA REV = 1
_
PCIE PORT BIFURCATION STRAPS
CFG[5:6]
[25,27,28,31,33,41,44,55]
[2,3,7,47]
[7,48,56]
[7,27,28,47,49,51]
[25,28,31,33,38,40,41,42,44,45,47,48,56]
3
2 1
11/9 remove
CFG0 R1349 *1K_04
11/9 remove
X
CFG3 R1352 *1K_04
CFG4 R1353 1K_04
CFG5
R1354 X 1K_04
CFG6 R1355 1K_04
_
CFG7 R1356 _ *1K_04
CFG8
_
X
x
11/9 remove
H_TDO R1372
CFG17 H_TCK R1378
_
CFG16
CFG19 x _
CFG18
x
x
SKL_XDP_MBP_0
x
SKL_XDP_MBP_1
SKL_MBP_2
x
SKL_MBP_3 H_SKTOCC#
x R1660
x
x _
H_TDO
H_TDI
H_TMS
x
H_TCK
x
x
H_TRST#_CPU
x
H_PREQ#_CPU
H_PRDY#_CPU
x
x
x
CFG_RCOMP
R1381
49.9_1%_04
_
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
CFG2
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
EMBEDDED DISPLAY PORT PRESENCE STRAP
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
0: ENABLED;
AN EXTERNAL DISPLAY PORT DEVICE
CFG4
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
DEFENSIVE PULL DOWN SITE
CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/
3.3VA
Title Title Title
[05] Processor 4/7-CLK/JTAG/MISC [05] Processor 4/7-CLK/JTAG/MISC [05] Processor 4/7-CLK/JTAG/MISC
VCCIO
1.0DX_VCCSTG
1.0V_VCCST
Size Size Size Document Number Document Number Document Number
VDD3 6-7P-N15F9-003 6-7P-N15F9-003 6-7P-N15F9-003
Custom Custom Custom
Date: Date: Date: Thursday, March 17, 2016 Thursday, March 17, 2016 Thursday, March 17, 2016 Sheet Sheet Sheet
2 1
D
1.0V_VCCST
51_04
51_04
3.3VA
10K_04
C
B
A
Rev Rev Rev
1.0 1.0 1.0
5 5 5 of of of 66 66 66