Power On Reset; Controller, I/O - ConMed Sabre 2400 Operators & Service Manual

The relay enable flag, /RLYEN-Q from U2-11, is
reset on power-up. This permits the microproces-
sor (U3) to test the WDT during initialization
without allowing RF to appear at the outputs.
While RLYEN-Q is disabled (low), the WDT will
not lock up, permitting the software to test for
correct operation. This is done by strobing the
WDT early, then late, and looking for the genera-
tion of the interrupt (Q2=0). The WDT is then
triggered within the correct time window (20 to
30 msec) and should result in Q2 remaining high.
If these results are obtained, the WDT timer cir-
cuitry is operating normally.
After initialization is complete, the microproces-
sor generates a WDSTR at the start of the first
normal program timing cycle. The relay enable
flag, /RLYEN-Q, is set by the NAND gate, U2-9
going low. After this, the program enters the nor-
mal operation program loop.
If a WDSTR is not generated within 34 msec of
the previous strobe, the second stage will time
out and Q2 will go low resulting in a WFAIL.
Since RLYEN-Q and /Q2 (U1-9) are high, the
inputs to U2-1 and U2-2 are both true resulting
in its output (U2-3) going low. This resets the
first stage one-shot. Now that Q1 (U1-6) cannot
go high, Q2 (U1-12) is prevented from being
retriggered. With the WDT Q2 output gone low,
the microprocessor will execute a WDT failure
interrupt routine in response to /INTO falling
and WFAIL will disable drive to the power ampli-
fier.
If the WDSTR is generated before 18 msec,
while Q1 is high, the NAND gate (U2-1 and U2-
2) will both be high resulting in U2-3 going low
and resetting the second stage. This causes the
same results as the late strobe described above.
Note that the signal which causes the WDT to
latch and ignore all subsequent WDSTR pulses
is RLYEN-Q being high. The only way to reset
RLYEN-Q is a Power On Reset.

3.1.3.2 Power On Reset

The Power On Reset (POR) circuit consists of a
single chip specifically designed for this function.
The POR circuit monitors +5 Vdc (U50-8) and
the output signals RST (pin 5) and /RS (pin 6)
become active if +5 Vdc falls below 4.75 Vdc.
The 8031 microprocessor operation is specified
down to 4.5 Vdc. This allows power supply mar-
gin for proper power down of the controller until
reset occurs. On power up, /RS is kept active for
a minimum of 250 msec to allow the power sup-
ply and microprocessor to stabilize.
One last feature of this circuit is its function as
a secondary Watchdog timer. This is enabled by
the connection of Address Latch Enable (ALE)
from the microprocessor (U3-30) to U50-7. The
RS and /RS outputs are forced to an active state
when the /ST input (U50-7) is not stimulated for
1.2 seconds. This function is not normally used
because it requires a failure in the microproces-
sor and the Watchdog Timer circuitry. This is
considered a double fault condition and the odds
of the two occurring simultaneously is very low.
Also, it is possible for ALE to continue in normal
operation while other parts of the microprocessor
are not. The WDT circuit described previously, is
used because it is not susceptible to this failure in
fault detection.

3.1.3.3 Controller, I/O

The four digital ports of the 8031 (U3) are func-
tionally assigned as follows.
PORT 0 (P0.0 - P0.7). This port serves two digi-
tal functions: 8-bit data bus for communicating
with external I/O, and low-order address bus for
accessing external Program Memory.
PORT 1 (P1.0 - P1.7). This port is dedicated to
discrete inputs or outputs. Port P1.0 and P1.1
are used to generate the serial signals necessary
to write or read to the calibration EEPROM U4.
Ports P1.2 and P1.3 communicate serially with
the Quad DAC U11 and Ports P1.4 and P1.5
with the 8 channel ADC U16 which converts
Current sense, Line sense and Return Monitor
voltages to digital form. Ports P1.6 and P1.7 pro-
vide clock and data lines for the display drivers.
R
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