Display Hardware; Keyboard; Power Amplifier - ConMed Sabre 2400 Operators & Service Manual

The current condition of the hand/foot controls
and the keyboard are continuously monitored.
When a valid request to change mode or power
level is received, the displays are updated to reflect
the change. When a valid request for RF activity
is received, the following sequence is performed.
1. The appropriate RF indicator lamp and tone
are activated.
2. The requested accessory output relay is closed.
3. The current limit fail-safe is set.
4. The power setting is used to retrieve waveform
and amplitude parameters from the calibration
memory which are then sent to the RF drive cir-
cuits.
5. RF output is enabled via /RFEN.
Self-tests are continuously performed during
operation to ensure the integrity and reasonable-
ness of hardware and software operation during
the working program execution. Failure of these
tests will result in a safe end-to-program execu-
tion (RF drive and all relays are disabled). A
display of HLP on the Cut power levels and a 1
KHz tone alerts the operator to the condition.
The appropriate error code is displayed on the
Coag Power level.

3.1.5 Display Hardware

The Sabre 2400 display uses LED and incandes-
cent lamp segment technology. Three HV5708
drive chips (U19, U20, and U21) each contain
a 32 bit shift register, latch and segment drive
function. Each lamp segment is turned on or off
corresponding to a logic one or zero on a drive
line. Each drive line is then buffered by a section
of one of the ULN2004A buffers on the display
board (A-7). The three HV5708 chips may be
considered as a 96 bit shift register driving a 96
bit latch. A 96 bit data stream of display data
(DISDATA) is downloaded to the shift registers
serially by clock DISCLK after which the data is
transferred to the latch sections by signal DISLE.
At power on reset, all HV5708 drive chips are
blanked during the reset period by a reset driver
ULN2003 (U13-F).

3.1.5.1 Keyboard

A membrane switch panel is integrally mounted
in the display. The switches form a 5x3 matrix
which is scanned by PIA U10 and debounced in
software.

3.1.6 Power Amplifier

The Power Amplifier (PA) is a hybrid cascode
amplifier made up of four high voltage bipolar
transistors and a low voltage power Mosfet. Refer
to Schematic 4.6. Bipolar transistors Q1-Q4 are
connected in parallel, with their emitters con-
nected together through resistors R17-R20. That
combination is then connected to the drain of
Q5. This combination makes up a fast, high-volt-
age amplifier that can be controlled by the com-
bination of the dc voltage VBASE, and the fixed
amplitude, variable pulse width signal, BGATE.
In the OFF condition, BGATE is near ground,
turning off Q5 so that no drain current can flow.
Thus no base or emitter current can flow in the
bipolar transistors. Turn-on commences with
BGATE rising rapidly to turn on the MOSFET,
forcing its drain low. Since the capacitors con-
nected to the bases of the bipolar transistors are
charged up, this results in a large pulse of base
current flowing in from the bipolar transistors
Q1-Q4, quickly turning them on and delivering
power to the output circuitry.
After turn-on, Q5 will be conducting hard and
the bipolar transistors will draw collector current
in proportion to their base current, which in turn
is controlled by VBASE.
Turn-off commences with BGATE quickly drop-
ping to nearly 0 V , shutting off Q5 and effectively
disconnecting the bipolar transistors' emitters
from the circuit. Collector current then flows
out of the bipolar transistors' bases into the base
capacitors until all of the charge stored in the
bipolar transistors during turn-on is washed out.
Then the bipolar transistors completely shut off,
ceasing power transfer to the output circuitry.
R
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