Program Memory, Eprom; Base Voltage Generator - ConMed Sabre 2400 Operators & Service Manual

R
PORT 2 (P2.0 - P2.7). This port supplies the
high-order address bus which reads from external
Program Memory and writes to external I/O. All
I/O is memory mapped so that distinct addresses
access specific devices. The system is configured
so that only one device is addressed at a time.
PORT 3 (P3.0 - P3.7). This port generates spe-
cial signals used to control the overall system.
Ports P3.0 and P3.1 are used for factory test only.
Port P3.2 is the watchdog fail interrupt. Port
P3.4 provides the relay enable strobe, Port P3.5
controls the Digital I/O chip U10 address space
for either Memory of I/O.
The Address Decoder (U7), is used to select
external I/O devices for reading and writing.
High-order address to the decoder inputs, (A10,
A11, and A12) cause the corresponding output
(Y0 - Y7) to go low. After the address decode
has stabilized, either /RD or /WR will go low to
execute a data transfer with the addressed device.
There are two Peripheral Interface Adapters (PIA)
U6 and U10. U6 is a general purpose digital I/O
device which is used to input the hand and foot
activation controls, control the relays and wave-
form generator and provide Watchdog Strobe and
VSENSE Disable. U10, in addition to providing
digital I/O also contains the tone generator fre-
quency divider and a 256 x 8 byte RAM memory.
The digital I/O functions control RF enable, chip
select, keyboard scan and display drive functions.

3.1.3.4 Program Memory, EPROM

The program used by the microprocessor is stored
in external memory, the 32 K byte X 8 EPROM
(U91). It is programmed and verified at the fac-
tory to ensure correct operation of the ESU. The
lower order address A0-A7 is latched into U8 by
line ALE. A0-A7 in combination with the higher
order address A8-A14 provides the total address
to the program EPROM U9. The EPROM
is enabled by line PSEN going low during an
instruction fetch. Address lines A13-A15 provide
memory mapped I/O decoding when PSEN is
high to select one of the two PIA devices.
3-4
The nonvolatile EEPROM memory U4 is a
serial device which stores calibration coefficients
and program presets. Validity of these values is
insured by also storing a CRC check sum anytime
these values are changed.
When the ESU is powered up, the data stored
in the non-volatile section of U4 is automatically
copied onto the static RAM where it is accessed
by the microprocessor via the address/data bus.

3.1.3.5 Base Voltage Generator

The base voltage generator is schematically
depicted on Schematic 4.3. It is microprocessor
controlled with two analog feedback paths that
can turn the base voltage down in case of exces-
sive power amplifier current or high output volt-
age. The high voltage shutback is divided down
to have a higher threshold in monopolar coag
mode.
The base voltage generator is made up of two sec-
tions of the Quad DAC (U11), an inverting sum-
ming amplifier (U12:A) and a power integrated
circuit Q6. The two DAC sections VOUTA and
VOUTB are resistively summed together to form
one 10-bit DAC which controls VBASE setting.
Q6 has internal current and temperature limit
shutdown. It cannot be checked by the standard
base-emitter and base collector diode checks with
a DVM.
The -ISENSE and IGND signals are developed in
the RF power amplifier on the Power Conversion
Board A1. These signals are generated by the
power amplifier supply current passing through
sense resistor A1R2. The resulting voltage
-ISENSE is proportional to the total dc current
used by the RF power amplifier. The portion of
U12 that includes pins 8, 9, and 10 makes up
a low pass filtered differential voltage amplifier
that amplifies the -ISENSE voltage. The resulting
ISENSE voltage is proportional to the dc cur-
rent drawn by the Sabre 2400 RF power ampli-
fier from the RF supply, RFSUP . When ISENSE
exceeds the voltage at U12-3 by a diode voltage
drop, the ISENSE feedback loop becomes domi-
nant and backs VBASE down to maintain the
RF power amplifier current at its limit. This is
independent of microprocessor control and is an
additional safety feature.