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The MPU DPLL power domain is switched off automatically by the PRCM only when the device enters the
OFF mode.
MPU subsytem power modes:
The major part of the MPU subsystem belongs to the MPU power domain. The modules inside this power
domain can be off at a time when the ARM processor is in an OFF or standby mode. IDLE/WAKEUP
control is managed by the clock generator block, but initiated by the PRCM module. The MPU standby
status can be checked with the PRCM.CM_IDLEST_MPU[0] ST_MPU bit.
For the MPU to be on, the core (referred here as the device core) power must be on.
The device power management does not allow INTC to go to OFF state when MPU domain is on (active
or one of retention modes).
The NEON core has independent power off mode when not in use. Enabling and disabling of NEON can
be controlled by software.
The MPU L1 cache memory does not support retention mode, and its array
switch is controlled together with the MPU logic. For compliance, the L1
retention control signals exist at the PRCM boundary, but are not used. The
ARM L2 can be put into retention independently of the other domains.
MPU retention modes are:
•
Open switch retention (OSwR)
•
Closed switch retention (CSwR)
These modes are described in
Table 4-14
outlines the supported operational power modes. All other combinations are illegal. The ARM
L2, NEON, and ETM/Debug can be powered up/down independently. The APB/ATB ETM/Debug column
refers to all three features: ARM emulation, trace, and debug.
Mode
MPU and
ARM L2 RAM
ARM Core
Logic
1
Active
2
Active
3
Active
4
Active
(1)
The L2 can be put into retention mode regardless of other voltage domain states. The combination of Cortex Logic active and L2 in
retention mode (modes 3 and 4) is legal, but would result in improper execution of instructions with referencing data from L2. This
combination must not be used.
SWPU177N – December 2009 – Revised November 2010
Public Version
Table
4-13.
Table 4-13. MPU Retention Modes
Name
Mode
ARM Logic
Dormant
OSwR
OFF
RET
CSwR
ON
Table 4-14. MPU Subsystem Operation Power Modes
NEON
Active
Active
Active
OFF
RET
Active
RET
OFF
Copyright © 2009–2010, Texas Instruments Incorporated
MPU Subsystem Functional Description
CAUTION
L1
L2
OFF
RET
ON
RET
MPU INTC
APB/ATB Debug Comments
and ETM
Active
Disabled or
enabled
Active
Disabled or
enabled
Active
Disabled or
enabled
Active
Disabled or
enabled
Functional active run mode (ETM
enabled mode when
emulation/debug required.
Production devices should have
ETM disabled).
Functional active run mode. NEON
disabled via SW; NEON is internally
clock gated.
(1)
Do not use; see
(1)
Do not use; see
MPU Subsystem
687
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