Camera Isp Histogram Process; Camera Isp Histogram White Balance Field-To-Pattern Assignments; Hist_Cnt; Hist_Wb_Gain - Texas Instruments OMAP36 Series Technical Reference Manual

Camera ISP Functional Description
6.4.8.2.2 Camera ISP Histogram Block Diagram
10 bits
RAW data
8 to 14 bits
RAW data
6.4.8.2.3 Camera ISP Histogram Input Interface
The histogram receives RAW image/video data from the video port interface through the CCDC (which is
interfaced to an external sensor) or from the read buffer interface through memory
SOURCE).
The input data is 10 bits wide if the source is the video-port interface. When the input source is from
memory, data-bit width can range from 8 to 14 bits. If the input data is 8 bits packed (memory contains
two 8-bit pixels for every 16 bits), the
for every 16 bits, the DATSIZ bit must be cleared.
Likewise, if memory contains one pixel for every 16 bits, the DATSIZ bit must be cleared. The input
memory address (HIST_RADD) and line-offset (HIST_RADD_OFF) registers are used to specify the
location of the input frame in memory. Both of these registers should be aligned on 32-byte boundaries.
The frame-input width and height are configured using the

HIST_H_V_INFO

[13:0] VSIZE register fields, respectively.
The histogram module supports 4-color Bayer color patterns. The
select the color pattern of the input data (Bayer).
6.4.8.2.4 Camera ISP Histogram White Balance
A white-balance gain can be separately applied to each color channel by programming the fields in the

HIST_WB_GAIN

register.
field in the WB_GAIN register.
Table 6-45. Camera ISP Histogram White Balance Field-to-Pattern Assignments
HIST_WB_GAIN fields
WG00
WG01
WG02
WG03
1226
Camera Image Signal Processor
Public Version
Figure 6-95. Camera ISP Histogram Process
Input interface
Video port
8 to 14
interface
bits
(CCDC)
Read
buffer

HIST_CNT[3]

interface
SOURCE
(SDRAM)
HIST_CNT
Table 6-45 indicates which pixel index in the color pattern corresponds to each
Bayer
0
1
2
3
Copyright © 2009–2010, Texas Instruments Incorporated
HIST_CNT[2:0]
SHIFT
White Bit
balance shift
[8] DATSIZ bit must be set. If memory contains one pixel
HIST_H_V_INFO
HIST_CNT
SWPU177N – December 2009 – Revised November 2010
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Histogram
binning
1024 x 20 bit
bin counter
memory
Histogram
memory
camisp-073
(HIST_CNT [3]
[29:16] HSIZE and
[6] CFA field is used to