Advertisement
Camera ISP Basic Programming Model
Figure 6-110. cam_strobe Signal-Generation for Red-Eye Removal
cam_strobe = PRESTROBE or STROBE
•
t1: Set by the
TCTRL_PSTRB_DELAY
•
t2: set by the
TCTRL_PSTRB_LENGTH
•
t5: set by the TCTRL_PSTRB_REPLAY[24:0] DELAY bit field. The number of times the pulse is
repeated is controlled by the
In the former example,
– The possible delay values are 0 to 2
The maximum signal duration is (2
– The possible count values are 0 to 127 additional pulses.
•
t3: Set by the
TCTRL_STRB_DELAY
•
t4: Set by the
TCTRL_STRB_LENGTH
6.5.6 Programming the CCDC
This section discusses issues related to the software control of the CCDC. It lists which registers are
required to be programmed in different modes, and describes how to enable and disable the CCDC, how
to check the status of the CCDC, the different register access types, and programming constraints.
6.5.6.1
Camera ISP CCDC Hardware Setup/Initialization
This section discusses the configuration of the CCDC required before image processing can begin.
6.5.6.1.1 Camera ISP CCDC Reset Behavior
On hardware reset of the camera ISP, all registers in the CCDC are reset to their reset values.
6.5.6.1.2 Camera ISP CCDC Register Setup
Before enabling the CCDC, the hardware must be correctly configured through register writes.
identifies the register parameters that must be programmed before enabling the CCDC.
1264
Camera Image Signal Processor
Public Version
cam_global_reset event
t1
PRESTROBE
STROBE
OFF
register
register
TCTRL_PSTRB_REPLAY
TCTRL_PSTRB_REPLAY
25
-1 cycle. The cycles are at the CNTCLK clock frequency.
25
-1) x 2.366 s = 79 s (TCTRL_CTRL[18:11] DIVC = 511).
register
register
Copyright © 2009–2010, Texas Instruments Incorporated
t2
t5
t3
ON
OFF
ON
OFF
ON
[31:25] COUNTER register.
[31:25] COUNTER = 2.
SWPU177N – December 2009 – Revised November 2010
www.ti.com
t4
OFF
ON
camisp-083
Table 6-61
Advertisement
Chapters
