Lpc; Lpc Boot - Kontron nanoETXexpress-SP User Manual

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4.2

LPC

The Low Pin Count (LPC) Interface signals are connected to the LPC Bus bridge, which is located in the . The LPC low speed

interface can be used for peripheral circuits such as an external Super I/O Controller, which typically combines legacy-

device support into a single IC. The implementation of this subsystem complies with the COM Express® Specification.

Implementation information is provided in the COM Express® Design Guide maintained by PICMG. Please refer to the

official PICMG documentation for additional information.

The LPC bus does not support DMA (Direct Memory Access).

This leads to limitations for ISA bus and SIO (standard I/O´s like Floppy or LPT interfaces) implementations. When more

than one device is connected to the LPC bus a clock buffer is required!

4.3

The nanoETXexpress-SP supports boot from an external Firmwarehub on LPC bus (LPC FWH). The external LPC FWH can be

activated with signal A34 „BIOS_DISABLE#":

» Pin A43 open: Boot from on-module BIOS

» Pin A43 ground: Boot from baseboard LPC-FWH

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