Ddsg And Dchg Pin Operation; Fuse Drive - Texas Instruments BQ769142 Manual

High accuracy battery monitor and protector for liion, li-polymer, and lifepo4 battery packs

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12.9 DDSG and DCHG Pin Operation

The BQ769142 device includes two multifunction pins, DDSG and DCHG, which can be configured as logic-level

outputs to provide a fault-related signal to a host processor or external circuitry (that is, DDSG and DCHG

functionality), as a thermistor input, a general purpose ADC input, or a general purpose digital output.

When used as a digital output, the pins can be configured to drive an active high output, with the output voltage

driven from either the REG18 1.8 V LDO or the REG1 LDO (which can be programmed from 1.8 V to 5.0 V).

Note: if a DC or significant transient current may be driven by a pin, then the output should be configured to drive

using the REG1 LDO, not the REG18 LDO.

When the pins are configured for DDSG and DCHG functionality, they provide signals related to protection faults

that (on the DCHG pin) would normally cause the CHG driver to be disabled, or (on the DDSG pin) would

normally cause the DSG driver to be disabled. These signals can be used to control external protection circuitry,

if the integrated high-side NFET drivers will not be used in the system. They can also be used as interrupts in

manual FET control mode for the host processor to decide whether to disable the FETs through commands or

using the CFETOFF and DFETOFF pins.

The FUSE pin on the BQ769142 device can be used to blow a chemical fuse in the presence of a Permanent

Fail (PF), as well as to determine if an external secondary protector in the system has detected a fault and is

attempting to blow the fuse itself. The pin can drive the gate of an NFET, which can be combined with the drive

from an external secondary protector, as shown in

BQ769142 device, it remains in a high-impedance state and detects a voltage applied at the pin by a secondary

protector. The device can be configured to generate a PF if it detects a high signal at the FUSE pin.

The device can be configured to blow the fuse when a PF occurs. In this case, the device will only attempt to

blow the fuse if the stack voltage is above a programmed threshold, based on a system configuration with the

fuse placed between the top of stack and the high-side protection FETs. If instead the fuse is placed between the

FETs and the PACK+ connector, then the device bases its decision on the PACK pin voltage (based on

configuration setting). This voltage threshold check may be disregarded under certain special cases, as

described in the BQ769142 Technical Reference Manual (SLUUCF2).

Figure

12-1. When the FUSE pin is not asserted by the

Figure 12-1. FUSE Pin Operation

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SLUSE91A – SEPTEMBER 2020 – REVISED FEBRUARY 2021

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