Spi Communications - Texas Instruments BQ769142 Manual

www.ti.com
SCL
A7 A6
SDA
Start
2
I C Read without Repeated Start
not available in hardware. For a block read, the master ACKs each data byte except the last and continues to
clock the interface. The I
When enabled, the CRC for a read transaction is calculated as follows:
• In a single-byte read transaction, the CRC is calculated beginning at the first start, so will include the slave
address, the register address, then the slave address with read bit set, then the data byte.
• In a block read transaction, the CRC for the first data byte is calculated beginning at the first start and will
include the slave address, the register address, then the slave address with read bit set, then the data byte.
The CRC resets after each data byte and after each stop. The CRC for subsequent data bytes is calculated
over the data byte only.
The CRC polynomial is x
When the master detects an invalid CRC, the I
to an idle state.
SCL
A7 A6
SDA
Start

14.3 SPI Communications

The SPI interface in the BQ769142 device operates as a slave-only interface with an optional CRC check. If the
OTP has not been programmed, the BQ769142 device initially powers up by default in 400 kHz I
other device versions will initially power up by default in SPI mode with CRC enabled, as described in the
Comparison Table. The OTP setting to select SPI mode can be programmed into the BQ769142 on the
manufacturing line, then when the device powers up, it automatically enters SPI mode. The host can also
change the serial communication setting while in CONFIG_UPDATE mode, although the device will not
immediately change communication mode upon exit of CONFIG_UPDATE mode to avoid losing communications
during evaluation or production. The host can reset the device or write the SWAP_TO_SPI() subcommand to
change the communications interface to SPI immediately.
Copyright © 2021 Texas Instruments Incorporated
...
A1 R7 R6
R/W ACK
Register
Slave Address
Address
2
Figure 14-2. I C Read with Repeated Start
shows a read transaction where a Repeated Start is not used, for example if
2
C block will auto-increment the register address after each data byte.
8 2
+ x + x + 1, and the initial value is 0.
2
C master will NACK the CRC, which causes the I
...
A1 R7 R6
R/W ACK
Register
Slave Address
Address
2
Figure 14-3. I C Read Without Repeated Start
Product Folder Links:
SLUSE91A – SEPTEMBER 2020 – REVISED FEBRUARY 2021
... ...
R0 A7 A6 A1
ACK
Slave Address
Repeated
Start
...
D7 D6 D0
ACK
Slave
Drives Data
...
R0 A7 A6
ACK
Stop Start Slave Address
...
D7 D6 D0
ACK
Slave
Drives Data
BQ769142
R/W ACK
...
C7 C6 C0
NACK
Slave
Stop
Drives CRC
(optional )
Master
Drives NACK
2
C slave to go
...
A1
R/W ACK
...
C7 C6 C0
NACK
Slave
Stop
Drives CRC
(optional )
Master
Drives NACK
2
C mode, while
Submit Document Feedback
BQ769142
Device
53