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BQ769142
SLUSE91A – SEPTEMBER 2020 – REVISED FEBRUARY 2021
Can be configured to have a weak pulldown to VSS or weak pullup to REG1 enabled continuously
ALERT, CFETOFF, DFETOFF, TS1, TS2, TS3, HDQ, DCHG, and DDSG
Thermistor temperature measurement
A thermistor can be attached between the pin and VSS.
ADCIN
Pin can be used for general purpose ADC measurement.
12.6 RST_SHUT Pin Operation
The RST_SHUT pin provides a simple way to reset or shutdown the BQ769142 device without needing to use
serial bus communication. During normal operation, the RST_SHUT pin should be driven low. When the pin is
driven high, the device will immediately reset most of the digital logic, including that associated with the serial
communications bus. However, it does not reset the logic that holds the state of the protection FETs and FUSE,
these remain as they were before the pin was driven high. If the pin continues to be driven high for 1 second, the
device will then transition into SHUTDOWN mode, which involves disabling external protection FETs, and
powering off the internal oscillators, the REG18 LDO, the on-chip preregulator, and the REG1 and REG2 LDOs.
12.7 CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
The BQ769142 device includes two pins (CFETOFF and DFETOFF) which can be used to disable the protection
FET drivers quickly, without going through the host serial communications interface. When the selected pin is
asserted, the device disables the respective protection FET. Note: when the selected pin is deasserted, the
respective FET will only be enabled if there are no other items blocking them being reenabled, such as if the
host also sent a command to disable the FETs using the serial communications interface after setting the
selected pin. Both the CFETOFF and DFETOFF pins can be used for other functions if the FET turnoff feature is
not required.
The CFETOFF pin can optionally be used to disable the CHG and PCHG FETs, and the DFETOFF pin can
optionally be used to disable the DSG and PDSG FETs. The device also includes the option to configure the
DFETOFF pin as BOTHOFF functionality, such that if that pin is asserted, the CHG, PCHG, DSG, and PDSG
FETs will be disabled. This allows the CFETOFF pin to be used for an additional thermistor in the system, while
still providing pin control to disable the FETs.
The CFETOFF or BOTHOFF functionality disables both the CHG FET and the PCHG FET when asserted.
The DFETOFF or BOTHOFF functionality disables both the DSG FET and the PDSG FET when asserted.
12.8 ALERT Pin Operation
The ALERT pin is a multifunction pin that can be configured either as ALERT (to provide an interrupt to a host
processor), a thermistor input, a general purpose ADC input, a general purpose digital output, or an HDQ serial
communication interface. The pin can be configured as active-high, active-low, or open-drain to accommodate
different system design preferences. When configured as the HDQ interface pin, the pin operates in open-drain
mode.
When the pin is configured to drive an active high output, the output voltage is driven from either the REG18 1.8
V LDO or the REG1 LDO (which can be programmed from 1.8 V to 5.0 V).
If a DC or significant transient current is driven by this pin, then the output should be configured to
drive using the REG1 LDO, not the REG18 LDO.
The BQ769142 device includes functionality to generate an alarm signal at the ALERT pin, which can be used
as an interrupt to a host processor. When used for the alarm function, the pin can be programmed to drive the
signal as an active-low or hi-Z signal, an active-high or low signal, or an active-low or high signal (that is,
inverted polarity). The alarm function within the BQ769142 device includes a programmable mask, to allow the
customer to decide which of many flags or events can trigger an alarm.
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