Timing" Tab - IBA ibaFOB-TDCexp Manual

ibaFOB-TDCexp

"Timing" tab

8.2.3
Here you'll find information about access of the card to the SIMATIC TDC CPUs and the
access of the card to the memory (DMA).
Figure 21:
Timing
These settings apply to the cycle times which are only relevant for the SD-TDC Request
system. For SD-TDC-lite cards all channels are assigned to cycle time T1 corresponding
to the ibaPDA time base.
The following sections provide essential information:
 Current transfer duration:
Duration of the transfer of one sample. The ratio of the "Current transfer duration"
to the smallest "Actual read cycle time" gives information about the load factor of
the ibaFOB-TDCexp card.
 Max. transfer duration:
Maximum duration of a data transfer since the last reset of the counters.
 Dropped transfers:
Number of dropped samples since the last reset of counters.
 Automatic channel initializations:
Diagnostic counter for automatic actions.
Note
You will find more information about the settings of cycle times in chapter 11.1
"Configuration of cycle times".
Timing
Manual
Issue 1.2
31