Xilinx Artix-7 FPGA AC701 Getting Started Manual page 12

Basic Hardware Bring-up with Built-In Self-Test
Run the BIST Application
1.
2.
3.
4.
5.
X-Ref Target - Figure 8
6.
7.
12
Download RDF0220 (AC701 BIST design files) from the web at
under the Docs & Designs tab.
Unzip the design files to the C:\ directory.
Open a Vivado Tcl shell: Start > All Programs > Xilinx Design Tools >
Vivado 2013.2 > Vivado 2013.2 Tcl Shell
Start the installed terminal program.
Select Setup > Serial Port... and ensure that the settings match those shown in
Figure 8:
• Baud Rate: 9600
• Data: 8 bit
• Parity: none
• Stop: 1 bit
• Flow control: none
In the Vivado Tcl shell, type:
source C:/ac701_bist/ready_for_download/bist_download.tcl
Select the desired tests to run and observe the test results (see
www.xilinx.com
Figure 8: Serial Port Setup
www.xilinx.com/ac701
UG967_08_111412
Figure 9).
AC701 Getting Started Guide
UG967 (v3.0) July 10, 2013