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Startup and Operation
Table 2-1. Processor Default View of the Memory Map (Continued)
2
Processor Address
Start
FEF90000
FEFF0000
FF000000
FFF00000
PCI Local Bus Memory Map
2-4
Size
End
FEFEFFFF
384KB
FEFFFFFF
64KB
FFEFFFFF
15MB
FFFFFFFF
1MB
Notes 1. Default map for PCI/ISA I/O space. Allows software to
determine whether the system is MPC105-based or
Falcon/Raven-based by examining either the PHB Device ID
or the CPU Type register.
2. The first 1MB of ROM/Flash Bank A (soldered 4MB Flash)
appears in this range after a reset if the rom_b_rv control bit in
the Falcon's ROM B Base/Size register is cleared. If the
rom_b_rv control bit is set, this address range maps to
ROM/Flash Bank B (socketed 1MB ROM/Flash).
For detailed processor memory maps, including suggested PREP-
compatible memory maps, refer to the MCPN750A CompactPCI Single
Board Computer Programmer's Reference Guide (part number
MCPN750A/PG).
The local PCI memory map is the PCI memory map as viewed by the
MCPN750A base board. This is also the secondary bus side of the 21554
on the MCPN750A. This map is controlled by the Raven ASIC and the
21554 PCI-to-PCI bridge. The Raven and the 21554 PCI-to-PCI bridge
have flexible programmable map decoder registers to customize the
system for a wide range of applications.
After a reset, the Raven ASIC map decoders are in their default state.
Software must program the appropriate map decoders for a specific
environment. The 21554 bridge map decoders default state is determined
by the SROM values loaded.
Definition
Not Mapped
Raven Registers
Not Mapped
ROM/Flash Bank A or Bank B
Computer Group Literature Center Web Site
Notes
2
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