Table of Contents
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Auto-Initialize of NVRAM Header En-
able
4-4
Bug or System explained
DRAM Parity Enable
DRAM Speed in NANO Seconds
Field Service Menu Enable explained
4-3
L2 Cache Parity Enable
Memory Size Enable
Memory Size Ending Address
Memory Size Starting Address
Network Auto Boot Abort Delay
Network Auto Boot at power-up
Network Auto Boot Configuration Pa-
rameters Offset
Network Auto Boot Controller LUN
Network Auto Boot Device LUN
Network Auto Boot Enable
Network PRep-Boot Mode Enable
NVRAM Bootlist Boot at Power-up only
4-5
NVRAM Bootlist Boot Enable
PCI Interrupts Route Control Registers
4-10
Primary SCSI Bus Negotiations Type
4-4
Primary SCSI Data Bus Width
Probe System for Supported I/O Con-
trollers
4-3
ROM Boot Abort Delay
ROM Boot at power-up only
ROM Boot Direct Ending Address
ROM Boot Direct Starting Address
ROM Boot Enable
4-7
ROM First Access Length
SCSI Bus Reset on Debugger Startup
secondary SCSI controller
Serial Startup Code LF Enable
Serial Startup Code Master Enable
PPCBug parameters
4-1
changing
4-1
configurable by ENV
http://www.mcg.mot.com/literature
prompt, debugger
PRST
4-3
4-10
push button reset
4-9
R
RAM
4-10
Raven ASIC
4-9
4-9
4-9
4-8
4-7
4-8
Raven MPU/PCI bus bridge controller ASIC
4-8
4-8
Raven/Falcon
4-7
4-4
real-time clock
registers
4-5
related specifications
remote command
remote control/status connector
remote interface
4-4
Remote Start
4-7
reset
4-7
4-7
4-7
4-9
4-4
RESET switch
4-4
4-11
resets
4-11
resetting the system
restart mode
4-3
3-11
as reset source
2-10
2-11
for timer functions
6-11
as MPIC Interrupt Controller
as MPU/PCI bus bridge controller 2-3,
6-20
general purpose timers
6-14
role in endian issues
2-13
Watchdog timers
6-15
2-12
role
2-3
6-11
configuration and status
B-4
channel
5-1
via cPCI bus
5-1
example
5-9
CompactPCI
2-11
power-on
2-11
software
2-12
undervoltage
2-11
Watchdog Timer
2-11
as hard reset
2-9
devices affected
2-10
2-9
3-12
2-8
6-8
6-16
N
D
IN-7
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E
X
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