The Reset Circuits - Racal Instruments 1260 Series User Manual

1260 Series User Manual
microprocessors memory map. This device also provides the
necessary DTACK\ or VPA\ signals for the microprocessor
depending on whether the selected device is a 16 bit device or a
6800 peripheral. LDTACK\ is an input to U23, and is used to
insert wait states when an Lbus cycle is accessed. The fourth
and final function provided by U23 is to detect an interrupt cycle
from the states of FC0\ and FC1\ and dropping the VPA\ line.
The microprocessor is configured to support up to seven
interrupts without requiring the polling of devices to determine
the interrupt. These seven sources are encoded onto three lines
by U108 which in turn drives the IPL0 - 2 lines of the
microprocessor.
All time dependent tasks are controlled by a counter\timer which
is a Motorola 6840 CTC. This is mapped as a 6800 peripheral.
The timer is configured by the microprocessor, and generates
interrupts at a programmed interval. During normal operation,
the timer is programmed to interrupt the microprocessor every 10
mS. Note the interrupt response latency of the microprocessor is
expected to vary by some small amount.
The microprocessor system has one general purpose input port,
and two general purpose output ports of 8 lines each. These
ports are mapped as part of the VXIbus interface and use 6800
timing. The input port, U110, is used to read the status of the
VXIbus interface state machine, and the status of the +24V on
the backplane in conjunction with U11b. This port also reads the
status of the VXIbus chassis receiver mechanism safety
switches, if fitted, and the checkin signal used to put the
microprocessor in self test mode. The safety switch input is
protected by R111, Q3 and Q4, while R112 acts as a pullup
when the switches are not used. U106 is an output port which is
used along with U1, U2 and U3 to select which VXIbus defined
TTLTRG line will be used to trigger the switching system. U109
is an output port to the VXIbus state machine that clears the
trigger input latch, the trigger output, and the check output used
in self-test mode.
The reset circuit provides a reliable signal under the most difficult

The Reset Circuits

situations. The circuit consists of a voltage reference, VR1, which
provides a nominal 1.23 voltage level, U11d, which senses when
the +5V supply drops below 4.5 volts and discharges the reset
timing capacitor, C2, via Q2. As the +5V supply is applied to the
board, the output of U11d is held low until the supply reaches a
nominal 4.75 volts, at which time it goes high. This signal is
inverted by U11c which in turn drives Q2. As long as the +5V
line is below +4.75 volts, the gate of Q2 is held high and prevents
C2 from charging. If, at any time the +5V supply drops below 4.5
volts due to the hysteresis provided by Z4d, the gate of Q2 is
Theory of Operation 4-4