Theory Of Operation; Power Suppliers; Microprocessor Block - Racal Instruments 1260 Series User Manual

1260 Series User Manual
Theory of
Operation

Power Suppliers

Microprocessor
Block
DC power for the 1260-01 is derived from the VXI backplane via
its host switch card. A +5V supply is used to operate all of the
logic on the Master and Slave boards. A +24V supply is used to
supply relay coil drive, and the +24V supply is monitored by
U11b on the 1260-01 to ensure the relay coil drive voltage is
available.
The microprocessor block accepts commands from the VXIbus,
interprets the commands and sends the required data to the
appropriate relay card via the Lbus interface. A simplified block
diagram is given in Figure 4-2. The microprocessor is a Motorola
MC68000 operating at 8 MHz. This block also contains ROM,
RAM, EEPROM,
counter/timer and general purpose input and output ports.
The program memory consists of two devices, U33 and U34.
These devices provide 64K by 16 (optionally 128K by 16) of
program memory as selected by W2. The OE\ of U33 and U34
is controlled by a PAL, U2, and programmed as follows:
MLOE\ goes low when R/W\ is high and LDS\ is low .
MHOE\ goes low when R/W\ is high and UDS\ is low.
The system RAM consists of U114 and U115. These devices
provide 32K by 16 of memory. The OE\ of U114 and U115 is
also derived from U24 in addition to their WR\ signals. U24 is
programmed as follows:
MLWE\ goes low when R/W\ and LDS\ are low .
MUWE\ goes low when R/W\ and UDS\ are low.
The EEPROM is an 8K by 8 device and is configured for 6800
peripheral timing. PWE\ goes low when R/W\ is low and the
clock E is high. The non-volatile memory's CE\ is qualified by
U21a with NVENB\ which is generated by the reset circuitry.
This prevents false writes to the EEPROM during power up and
power down sequences ensuring memory integrity. The time
delay between writes to the EEPROM is controlled by the system
software.
Address decoding is performed by a PAL, U23. This device
provides the necessary logic to map the other devices into the
address decoding,

Theory of Operation 4-3

interrupt logic, a