The Lbus Interface - Racal Instruments 1260 Series User Manual

The Lbus Interface

Theory of Operation 4-6
Data Low Register
Event Register
Logical Address Register
TTLTRG lines are used by external devices to open and close
the signal paths, as specified by previously received SLIST
commands from the Slot 0 controller. Each of the TTLTRG lines
corresponds to a different "channel" number.
The microprocessor selects TTLTRG lines through address
decoder U113, register 4106, and multiplexers U1 and U3. U1 is
used for output, while U3 is used for input. U2 is a buffer which
drives the selected output TTLTRG lines.
The Lbus interface
microprocessor controls the relay cards in the system. It is a
state machine which transmits the microprocessor's address and
data serially through the Lbus to the switching modules in the
switching system. The state machine makes the transfer of data
to and from the relay latches look as though they are memory
mapped in the microprocessors address space, and because of
the ability to add wait states to the microprocessors's bus cycle,
this process is entirely transparent to the user.
The Lbus interface state machine is implemented in a master
and slave configuration, where the master is part of the
microprocessor card and slaves are part of each relay card. The
master state machine is implemented in two 22V10 PALs, three
shift registers and three differential line drivers.
primary state machine and controls the state transitions for all
data transfer activities. The master state machine has 27 states,
where state S0 is the dormant state. When the state machine
detects that its select line (LBUS\) and AS\ input are both low, it
will proceed to state S1; otherwise it will remain at state S0.
During state S1, LD/SH\ is lowered and the 13 lowest address
lines are loaded into U22 and U112. During states S2 and S14,
the address data is shifted through a multiplexer, U13, and line
driver U4 onto the Lbus. This data is received by all relay cards
in the system, and the four most significant bits of the 13 are
used to select a specific card.
If the microprocessor was executing a write cycle, the data would
be loaded into data shift register U12 during state S1. This
register would be held in its hold mode until state S18 where it is
allowed to shift its contents out via the multiplexer, U13, and line
driver U4 to the Lbus. Alternatively, if the microprocessor was
executing a read cycle, then data shift register U12 would shift in
1260 Series User Manual
is the vehicle through
U9 and U101
U20
U102
which the
U14 is the