Emerson ATCA-F120 Installation And Use Manual page 81

The main features of the CPU are as follows:
On-die L1 cache
On-die L2 cache
DDR2 memory controller and interface
Local bus controller and interface
DUART
Programmable interrupt controller
Two 32-bit/66 MHz PCI buses
x1 PCI Express interface to RTM
4-channel DMA controller
Four 10/100/1000 GBit Ethernet MACs
Two I2C controller
Security engine
XOR engine
JTAG interface
Watchdog (not used on ATCA-F120)
4.4 Main Memory
The memory controller resides inside the MPC8548E PowerQUICC III CPU. The memory bus is
64 bit wide and ECC protected. It connects the CPU to the on-board memory modules. The
memory data bus runs at a maximum frequency of 266 MHz providing a total bandwidth of
4.267 GBytes/s.
The ATCA-F120 supports up to 1 GByte of main memory.
4.5 Glue Logic FPGA
The ATCA-F120 provides a Glue Logic FPGA which is used for various purposes. Details are given
in the following two subsections.
ATCA-F120 Installation and Use (6806800D06F)
Functional Description
81