NEC UPD98413 User Manual page 64

(c) Descramble of ATM cell
In the cell synchronization status, the data of the cell is descrambled by the following polynomial. The range of
descramble is limited to the payload of the cell.
43
Polynomial G (X) = X
An option mode in which the descrambling of cells can be disabled for testing purposes is supported. To set this
mode, use the CSCM bit of the MDATMR register.
(d) Dropping idle and unassigned cells
If an idle cell is detected as a result of monitoring the high-order four bytes of the header of the cell stream
extracted from a frame, the cell is not stored into the receive FIFO but is dropped. Patterns other than the
VPI/VCI field of the header to be monitored can be changed by using the DCHP register, so that an unassigned
cell can be dropped or passed along with the idle cell.
In the default, only CLP bit of the COMP field is set to "1", therefore only idol cell is dropped. (Unassigned cell is
not dropped.)
15
GFC3 GFC2 GFC1 GFC0
COMP Field
CLP Bit
×
1
0
(e) Output of cell from ATM interface
If cell synchronization is established, a cell that does not fit in the pattern specified by the DCHP register is stored
to the receive FIFO as a valid cell. The stored cell is transferred to the ATM device via the ATM interface. If a
cell is received when the receive FIFO is full, a receive FIFO overflow error occurs and that cell is dropped. The
occurrence of the receive FIFO overflow error can be used as an interrupt cause.
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CHAPTER 3 FUNCTIONAL OUTLINE
+ 1
Figure 3-19. DCHP Register
PTI2 PTI1 PTI0 CLP
COMP
DCHP Register Setting Examples
MASK Field
CLP Bit
1 Idle and unassigned cells
0 Idle cells only (default)
0 Unassigned cells only
PRELIMINARY
8 7
GFC3 GFC2 GFC1 GFC0
MASK
Cells to Be Dropped
0
PTI2 PTI1 PTI0 CLP
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