NEC UPD98413 User Manual page 21

POS Interface
Pin Name Serial No.
RFCLK
RDAT[31:0]
RSOP
RENB_B
RPRTY
REOP
RMOD[1:0]
CHAPTER 2 PIN FUNCTION
Address No. I/O Level
I
LVTTL
O
LVTTL
O
LVTTL
I
LVTTL
O
LVTTL
O
LVTTL
O
LVTTL
PRELIMINARY
Function
Receive FIFO read clock.
Clock signal of up to 104 MHz, supplied from the POS
device.
All signal operations in the data transfer of the reception
interface are executed in synchronization with this clock
signal.
Receive packet data bus.
32-bit data bus for outputting receives packets. Receive
data is output at a rising edge of RFCLK.
If RSX is high at the start of transfer, RDAT[7:0] is used to
specify the port address.
Receive start of packet.
Signal indicating the start position of a receive packet.
When RSOP is high, the data on RDAT is assumed to be
the beginning of a packet.
Receive read enable
Signal used by the POS device to request a transfer
interrupts. When RENB_B is low, the µPD98413 updates
the RDAT, RMOD, RSOP, REOP, RERR, RPRTY, RVAL,
and RSX signals at the next clock pulse. When RENB_B
µ
is high, the PD98413 will remain unchanged the RDAT,
RMOD, RSOP, REOP, RERR, RPRTY, RVAL, and RSX
signals at the next clock pulse.
Receive bus parity.
When receive packet data is to be output from RDAT, odd
or even parity data is generated and output from RPRTY.
Receive end of packet.
Signal indicating the end position of a receive packet.
When REOP is high, the data on RDAT is assumed to be
the end of a packet, and the effective bytes of the last
word are indicated by RMOD.
Receive word modulo.
Signal indicating the effective bytes of the last word RDAT
of a receive packet. RMOD is valid when REOP is high.
When RMOD[1:0] is equal to 00, RDAT[31:0] is effective.
When RMOD[1:0] is equal to 01, RDAT[31:8] is effective.
When RMOD[1:0] is equal to 10, RDAT[31:16] is effective.
When RMOD[1:0] is equal to 11, RDAT[31:24] is effective.
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