NEC UPD98413 User Manual page 112

(1) Synthesizer PLL
The internal synthesizer PLL generates the 622.08-MHz clock based on the 77.76MHz clock. All the ports
use this clock as there transmit clock. The internal synthesizer PLL starts creating a clock as soon as
power is applied. However, about
each port.
(2) Reference Clocks
µPD98413 provides two types reference clock input, a differential PECL reference clock input and a
LVTTL reference clock input. Both reference clock are internally ANDed to generate the reference for TxPLL
and CDR. If the LVTTL reference clock is used, the positive side of the differential PECL (RFCKPLT) must
be connected to a logic one and the negative side (RFCKPLC) to a logic zero. If a differential PECL
reference clock is used, LVTTL reference clock input (RFCKTTL) must be tied high.
(3) Loop timing mode
When the LPTIM bit of the MDPGEN register are set to 1, the corresponding port uses the clock extracted
by the CDR from the receive data as the transmit clock. This setting is made for each port and does not
affect the transmit clock setting of the other ports.
TDOT0/
TDOC0
RDIT0/
RDIC0
CD0
112
CHAPTER 4 INTERFACES
T.B.D ms must elapse before appropriate 622.08MHz clock is supplied to
Figure 4-2. Loop timing mode
Lock state
CDR
BIASC0 LPFC0 LPFCGND0
PRELIMINARY
MUX 0
8:1
DEMUX 0
1:8
CD
CNT
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