Access Timing - NEC UPD98413 User Manual

4.8.2 Access timing

When CS_B is asserted, AD [31:0], UWE_B, and R/W_B are loaded in synchronization with the rising of MCLK, and
the register at the address indicated by AD [31:0] is accessed.
Write operation
If R/W_B is low, a write operation is started. The data on AD [31:0] is loaded in synchronization with the next rising
of MCLK, and RDY_B is asserted when the operation in the next bus cycle is ready. When the write operation is
ended, the µPD98413 negates RDY_B, and RDY_B goes into a high-impedance state at the next rising of MCLK.
When the µPD98413 negate RDY_B, the microprocessor can deassert CS_B. The microprocessor must deassert
CS_B at least 1clock cycle.
MCLK(
AD[31:0](I/O)
CS_B(
UWE_B(
R/W_B(
RDY_B(
Read operation
If R/W_B is high, a read operation is started. When data output is ready, the data is output to AD[31:0] in
synchronization with the rising of MCLK, and RDY_B is asserted. When the microprocessor has received the data,
the µPD98413 negates RDY_B, and AD[31:0] go into a high-impedance state. At the next rising of MCLK, RDY_B
goes in to a high-impedance state. When the µPD98413 negate RDY_B, the microprocessor can deassert CS_B.
The microprocessor must deassert CS_B at least 1clock cycle.
CHAPTER 4 INTERFACES
Figure 4-25. Write Access Timing
I)
Address Data
I)
I)
I)
O)
Figure 4-26. Read Access Timing
PRELIMINARY
Address
NEC confidential and Proprietary
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