Transmit Atm Function - NEC UPD98413 User Manual

3.2.1 Transmit ATM function

(a) Cell data reception from ATM device
A cell is received from the high-end ATM device via the ATM interface of 32 bits × 104 MHz MAX and stored to
the transmit FIFO, having a capacity of 1K bytes for each port.
Items, below, are related to the mode setting and function of the transmit ATM interface. For details of the ATM
interface, see Section 4.2.
Selecting format of transmit cell
As the format of the transmit cell that is to be input to TXDATA[31:0], a 52-byte mode that does not include
one word of an HEC field, a 56-byte mode that includes one word of an HEC field, and formats in which a
TAG field is, or is not, inserted are supported. Before starting the insertion of a cell, the cell format must be
matched with the setting of the MDAPIT registers. For details of cell format, See Section 4.2.2.
Setting condition to deassert TXCLAV signal that indicates that cell reception is ready
If the transmit FIFO has a vacancy, the TXCLAV signal is asserted to inform the ATM device that the
µ PD98413 is ready to receive the next cell. If the transmit FIFO is full and the µ PD98413 cannot receive the
next cell, the TXCLAV signal is deasserted. The number of words (32bit) in the transmit FIFO at which the
TXCLAV signal is deasserted can be selected by using the APHIGH[7:0] bits of the FTHT1 register. This
setting is useful for connecting an ATM device that cannot immediately stop cell transfer after recognizing
that TXCLAV has been deasserted.
Detection of transmit FIFO overflow error
When a transmit FIFO is full and µ PD98413 receives next cell, µ PD98413 indicates the detection of a
transmit FIFO overflow error. The received cell data is ignored and not stored to the transmit FIFO after
transmit FIFO overflow occurs. If the transmit FIFO has a vacancy, the detection of the overflow is cleared.
Parity check
At the transmission side of the ATM interface, parity check is performed based on the cell data input to
TXDATA[31:0] and parity bit input to TXPRTY. The range of this check is up to when TXENB_B is asserted.
The parity is not checked when no cell is input. If a parity error is detected, the PARE bit of the APIET
register is set. In the default mode, odd parity calculation is performed, but an even parity can also be used
as an option by using the PARM bit of the MDAPIT register.
In addition, the µ PD98413 also checks the parity of the data that passes through the transmit FIFO as a self
check of its operation. If an error is detected, the PnPEB or PnPEA (n: port No.) bit of the APIPET register is
set.
(b) Generation/insertion of HEC
CRC operation is performed on the high-order four bytes of the five bytes of the header of an ATM cell. The
value resulting from the operation plus "55H" is inserted to the fifth byte position of the ATM header to carry out
HEC (Header Error Control). This HEC Generation can be disabled by the HECO bit of the MDATMT register. If
HEC generation is disabled and not inset HEC from ATM device, the HEC Field of ATM Cell is inserted "00h".
And if HEC generation is disabled and HEC is inserted from ATM device, the HEC field of ATM Cell is inserted
the original value that inserted from ATM device.
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Polynomial G (X) = X + X
CHAPTER 3 FUNCTIONAL OUTLINE
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+ X + 1
PRELIMINARY
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