Table of Contents
Advertisement
6.4 Operation Description
6.4.1 TAP Controller
The TAP controller is a circuit having 16 states synchronized with changes of the JMS and JCK pins. Its operation is
specified by IEEE Standard 1149.1.
6.4.2 TAP Controller State
Figure 6-2 shows the state transition of the TAP controller. The state of the TAP controller is determined depending
on the state of the JMS pin signal input at the rising edge of the clock input to the JCK pin. The operations of the
instruction register, boundary scan register, and bypass register change at the rising or falling edge of the clock input
to the JCK pin. (See Figure 6-3).
(1) Test-Logic-Reset
Ｌ
H
(2) Run-Test/Idle
Ｌ
Remarks 1. "H" and "L" of the arrows indicating state transition in the above figure indicate the state of the JMS pin
at the rising edge of the clock input to the JCK pin.
2. Numbers in ( ) in the above figure correspond to the explanation below.
308
CHAPTER 6 JTAG BOUNDARY SCAN
Figure 6-2. State Transition of TAP Controller
Ｈ
(3) Select-DR-Scan
Ｌ
H
(5) Capture-DR
Ｌ
(6) Shift-DR
Ｌ
H
(7) Exit1-DR
L
(8) Pause-DR
Ｌ
H
Ｌ
(9) Exit2-DR
H
(10) Update-DR
Ｌ
H
PRELIMINARY
H
(4) Select-IR-Scan
Ｌ
H
(11) Capture-IR
Ｌ
(12) Shift-IR
H
H
(13) Exit-IR
Ｌ
(14) Pause-IR
H
Ｌ
(15) Exit2-IR
Ｈ
(16) Update-IR
H
NEC confidential and Proprietary
H
Ｌ
H
Ｌ
Ｌ
Advertisement
Table of Contents
