NEC UPD98413 User Manual page 158

(5) Clearing the detailed cause register
The set bits of the detailed cause registers are cleared by CPU access. These bits may be cleared by reading or
writing. Whether to clear by reading or writing can be specified for each bit. Each detailed cause register has
three addresses: read clear, write clear, and read clear enable.
(a) Read clear
To clear a bit once it has been read, write 1 to the corresponding bit position at the read clear enable
address. When the read clear address is read, only the bit for which 1 has been written to the corresponding
bit position at the read clear enable address is cleared to 0. The bit that is disabled from being cleared by
the read clear enable register is not cleared. In default mode, all the bits can be cleared once they have
been read.
(b) Read only / Write clear
After reading the contents of a register, write 1 to the bit position in the register corresponding to the bit to be
cleared. When write 0 to the register, the content of register is not clear.
Clear
Contents display
Access Destination
Read clear address
Read only / Write clear address
Read clear enable register
Mask register
158
CHAPTER 4 INTERFACES
Figure 4-29. Detailed Cause Register Clearing Method
Read clear address
Read only / Write clear address
Read clear enable register
Setting
Mask register
Table 4-12. Functions of the Interrupt Cause Registers
This address is used for reading the contents of the register and then for
clearing the register. Note that only those bits enabled in the read clear
enable register are cleared to 0. Any attempt to perform write access to this
address is ignored.
This address is used to read the contents of the register and used to write-
clear the contents of the register.
Write the address so that 1 written over the bit to be write-cleared.
This register is used to enable or disable the read clear operation on a per-
bit basis. Only those bits set to 1 in this register are cleared to 0 when read
access to the read clear address is performed. By default, all the bits are
set to 1 (enable).
This register is used to mask or unmask each interrupt cause. Masking the
detailed cause register masks reflection on the PICR register, and masking
of the PICR register masks asserting the interrupt signal active. By default,
all the bits are set to 1, meaning that all the interrupt causes are masked.
PRELIMINARY
Detailed cause register
Register
Description
NEC confidential and Proprietary