NEC UPD98413 User Manual page 121

(2) Status polling (Multi-PHY operation with 1 TXCLAV)
In the status-polling mode, the ATM device can receive the µPD98413 port FIFO status information through the
polling mechanism. In this mode, only TXCLAV0 is used. TXCLAV1-3 are not used, and these signals are fixed
to low.
The ATM device can send a cell to the µPD98413 only when the port has indicated to the ATM device that it is
ready to receive at least one complete cell. The µPD98413 sends transmit cell buffer available information for
that port to the ATM device when that port is polled, using the TXCLAV0. Once the TXCLAV0 response for a
particular port indicates buffer availability, responses to subsequent polls of that port continues to indicate buffer
availability until after the second cycle of the transfer of a cell to that port. The FIFO availability information
indicated by TXCLAV0 is programmable by the FTHT register.
The ATM device polls by presenting the port address on TXADDR[1:0]. The µPD98413 responds two clock
cycles later by driving TXCLAV0 high if the port can accept one or more complete ATM cells; TXCLAV0 is driven
low otherwise. The TXCLAV0 is not applicable on the first cycle after TXSOC is asserted, on this cycle, the
µPD98413 keeps the status before the transfer is started.
TXADDR[1:0] during the clock cycle before asserting the TXENB_B signal will select the port which will receive
the next cell. The µPD98413 will decode this signal and the specified port will be ready to receive cell data from
the ATM device at the next clock cycle.
The following figure shows an example of the transmit timing in the status polling.
TXCLK
TXADDR[1:0]
PORT0 PORT1 PORT2
TXCLAV0
PORT0
TXENB_B
TXDATA[31:0]
P3 P4
TXPRTY
TXSOC
X : Invalid
Back-to-back transfer of cells is possible when two cells have to be sent the same port and this port indicates
that it can receive the second cell. In the case of back-to-back transfer the ATM device implicitly reselects the
µPD98413 port by leaving the TXENB_B asserted during the next to the last cycle of the cell transfer. The
second cell is transferred immediately after the previous one and the TXSOC is asserted to indicate the start of
cell. This example is illustrated below.
CHAPTER 4 INTERFACES
Figure 4-7. Transmit Timing (Status Polling)
PORT3
PORT1 PORT2 PORT3
P5 P6 P7 P8 P9
PRELIMINARY
PORT1
P10 P11 P12 X H1
X
NEC confidential and Proprietary
X
P1 P2 P3 P4
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